Eric M. Vogel

Rapid differential scanning calorimetry (DSC) measurements were performed on Ti, TiN, TiAl, and AlN multilayers that were magnetron sputtered at ambient temperature and had a similar overall composition to MAX-phase Ti2AlN. The DSC yielded thermal scans with exotherms indicating diffusion and crystallization processes during the annealing process, including the formation of Ti2AlN. Multilayer Ti/AlN yielded a distinctly large exotherm in the range of 500–700 °C, in contrast to the other films, and was estimated to have the highest cumulative enthalpy during annealing up to 700 °C. X-ray diffraction measurements and annealing treatments also indicated that all TiAlN films yielded Ti2AlN by 600 °C, with STEM imaging revealing the onset of Ti2AlN-like structural ordering in Ti/AlN by 475 °C. These data collectively show that multilayer films with Ti/AlN chemistry are distinctly reactive, experiencing phase transformation events that facilitate MAX-phase Ti2AlN synthesis at low substrate temperatures.

High‐resolution printing offers promising avenues for packaging micro‐ and nanoscale modular electrical components, enabling hybrid, high‐performance circuits. The miniaturization of component interfaces imposes stringent requirements on printed interconnect resolution, conductivity, and structural robustness. This work systematically investigates the fabrication and characterization of submicron‐to‐micron scale (300 nm–3 ) metal nanoparticle interconnects, focusing on the interplay between printing parameters, multilayer deposition, and thermal sintering conditions. Silver (Ag) and gold (Au) colloidal inks are printed with controlled cross‐sectional geometries and sintered under dry air, forming gas, and nitrogen atmospheres. Correlations between geometry, sintering atmosphere, and interconnect resistivity reveal that oxygen‐rich and reducing environments promote nanoparticle coalescence, while resistivity and long‐term stability are strongly dependent on cross‐sectional area. Optimized processing yields Au interconnects with widths down to and resistivity of . Integration with micromodular transistor circuits demonstrates that interconnect geometry and device interface quality strongly influence series resistance, and analysis of failure modes identifies strategies to improve reliability. These results establish a framework for designing electrically robust, high‐resolution printed interconnects, enabling reliable integration into next‐generation microelectronic packaging and hybrid interconnection technologies.

Since the initial synthesis of van der Waals 2D indium selenide is first documented in 1957, five distinct polymorphs and their corresponding polytypes are identified. In this study, a unique phase of indium selenide is reported via Scanning Transmission Electron Microscopy (STEM) analysis in the synthesized large‐area films – which is named the phase. The quintuple layers of the phase, characterized by a unique zigzag atomic configuration with unequal indium‐selenium bond lengths from the middle selenium atom, are distinct from any other previously reported phase of indium selenide. Cross‐sectional STEM analysis has revealed that the layers exhibit intralayer shifting. It is found that indium selenide films with layers display electric‐field‐induced switchable polarization characteristic of ferroelectric materials, suggesting the breaking of the inversion symmetry. Experimental observations of nonlinear optical phenomena – Second Harmonic Generation (SHG) responses further support this conclusion. This study reports a phase of indium selenide showing ferroelectricity over large areas at room temperature in a low‐dimensional limit.

Bottom-up synthesis of nanowires presents attractive prospects in the scaled manufacturing of electronic devices. Vapor–liquid–solid (VLS) growth of semiconductor nanowires is enabling in this regard; however, VLS growth can result in non-uniform doping, surface impurities, and other process-related imperfections that degrade the performance of nanowire transistors. In this study, we combine current–voltage measurements with an analytical model to explore the process–structure–property relationships of Si nanowire field effect transistors. We find that a simple surface etch results in improved subthreshold slope, on–off ratio, and effective mobility. Analytical modeling suggests that the improved performance is a result of reduced fixed charges and improved surface roughness at the oxide–silicon interface. These carrier scattering mechanisms provide critical insights necessary to eliminate process related defects and obtain high performance devices.

Micromodular metal-HfOx-metal resistive random-access memories (RRAM) were fabricated, transferred to foreign substrates, and contacted using high-resolution electrohydrodynamic jet (e-jet) printing. The modular RRAM exhibited bipolar switching at low operating voltages and multi-level analog resistance states programmable using variable amplitude voltage pulses. These variable resistance RRAMs were also integrated with an amplifier and a bandpass filter to modulate their gain and corner frequencies. This work enables integration of high-quality RRAM devices in modular circuits and paves the way for microscale heterogeneous integration at the device level.