Salvatore M. Amoroso

In Part II of this article we discuss the impact of a discrete treatment of traps on 3-D nand Flash random telegraph noise (RTN). A higher RTN results when discrete traps are taken into account, that can only be explained by a stronger influence of the discrete charged traps on the current conduction, leading to more percolation. The effects are then investigated as a function of the cell parameters, showing that a continuous model for traps cannot reproduce the correct dependence.

In this two-part article we discuss the difference between a continuous and a discrete approach to trap modeling in the simulation of 3-D nand Flash memories with polysilicon channel. In Part I we focus on threshold voltage (VT) fluctuations induced by traps and show that lower values for the average and rms VT arise when the discrete nature of traps is accounted for. We explain such differences in terms of a stronger percolation that leads to a lower number of filled traps in the discrete-trap case, and investigate such differences as a function of cell parameters and temperature. Finally, we compare the two approaches showing that a continuous trap model cannot reproduce the correct dependences resulting from a discrete treatment.

We present a dynamic random access memory (DRAM) design technology co-optimization (DTCO) methodology that allows the optimization of the DRAM cell structure in the presence of contact resistance variation, trap-assisted tunneling (TAT) leakage variation, and storage node capacitance variation. We showcase our methodology features and results by studying the optimization of a DRAM metal gate work function under the constraints of writeability, retention time (tRET) performance, and robustness to the row hammer effect. Our simulation results show that DRAM performance and its reliability are strongly affected by the contact resistance variations induced by random discrete dopants (RDDs) and can be maximized by means of DTCO-based engineering of contact area and doping concentrations. Our findings also highlight that focusing the optimization on leakage reduction can pay higher dividends than increasing storage node capacitance or improving writeability.

As an important constraint on the threshold voltage (V _t ) distribution, the random telegraph noise (RTN) has attracted much attention due to the widely used multi-bit-per-cell technology in 3D NAND flash. This work investigated the physical mechanisms of RTN in charge- trap-based 3D NAND flash. According to statistical 3D TCAD simulation analysis, the fringing field from the control gate and the random discrete nitride trapped charges, two competitive mechanisms, are proposed to be responsible for the non-monotonic RTN behavior. As the programmed cell V _t level increases, the increasing fringing field from the control gate reduces the current-path percolation effect and the RTN amplitude. However, once the random discrete nitride trapped charges start to dominate the percolation current path, the RTN amplitude increases significantly. Instructively, the clarification of RTN competitive mechanisms contributes to compacting V _t distributions specifically in multi-level 3D NAND flash.

Variability in nanoscale transistors poses significant challenges to CMOS technology development and circuit design. How to characterize, model, and evaluate variability and its impact at various levels of development at a particular CMOS generation has been critical for reducing cost and risk of the developing next generation of devices. In this chapter, we describe in great detail the simulation studies and developments of TCAD-based variability-aware design technology co-optimization (DTCO) methodology for the latest finFET technology. More specifically, using the 14 nm SOI finFET as a test vehicle, we show how different sources of variability influence the performance of finFETs and corresponding 6T-SRAM cells. In order to highlight the features and importance of TCAD-based variability-aware DTCO process, the simulations of variability, statistical compact model extraction and generation, and 216stochastic circuit simulations and verifications have been included in this chapter.

In this work we present a modeling study of a conceptual low power non-volatile memory cell based on inorganic molecular metal oxide clusters (polyoxometalates (POM)) as a storage media embedded in the gate dielectric of a Fully Depleted SOI (FD SOI) with reduced statistical variability. The simulations were carried out using a multi-physics simulation framework, which allows us to evaluate the variability in the programming window of the molecular based flash cell with an 18 nm gate length. We have focused our study on the threshold voltage variability influenced by random dopant fluctuations and random special fluctuations of the molecules in the floating gate of the flash-cell. Our simulation framework and conclusions can be applied not only to POM-based flash cell but also to flash cells based on alternative molecules used as a storage media.