Liangliang Lu

This paper proposes a digital predictive peak current control (PPCC) strategy for superbuck converters. The proposed strategy incorporates a current predictor to calculate the output current and a peak current controller to calculate the required duty ratio for the next switching cycle. The duty ratio is precalculated ahead of a switching cycle, which creates a switching cycle for signal samplings and digital calculations. At the end of the next switching cycle, the output current peak value is regulated to match the reference value. The proposed strategy regulates the output current peak value to the reference value within two switching cycles. This increases the current loop bandwidth to π/T rad/s, which optimizes the transient performance. Moreover, a new damping parameter design method based on the damping ratio is given. Furthermore, a simplified version is proposed to facilitate digital realization. This version directly calculates the required duty ratio, which significantly reduces digital calculations. Finally, the experimental results demonstrate the effectiveness of the proposed control strategy in improving the transient performance of the superbuck converter.

This paper proposes a current balancing loop that is obtained using the threshold median adjustment (TMA-CBL) to achieve the accurate current balancing of an interleaved constant frequency hysteresis (CFH) buck converter. The CFH control is implemented with a frequency phase loop based on a threshold width adjustment (TWA-FPL). To ensure the loop’s stability and minimize the steady-state error, a multi-phase, coupled, small-signal model (MPC-SSM) is derived with a consideration of the coupling effect among the multiple phases. Furthermore, the current balancing error is analyzed in detail, with a consideration of the sensing resistance deviations in the loop. Finally, based on a 180 nm BCD process, a four-phase interleaved buck converter is fabricated to verify the effectiveness of the proposed TMA-CBL. The maximum current balancing error is within 0.68% when the sensing resistors are deviated by 5%.

For multiphase voltage regulators (MPVRs) with conventional phase shedding and transient voltage clamping (TVC), transient response is limited by intrinsic clamping error, reduced converter loop feedback and phase shedding delay. To address the issues, this article proposes differentiation-triggered TVC (DTVC) and quasi-zero-delay phase shedding (QZDPS) schemes for joint transient enhancement of the MPVR. To eliminate the intrinsic clamping error, the DTVC scheme adopts a d v /d t circuit to detect output voltage differentiation in advance. Besides, converter load response is accelerated by saturated drive modulation in synchrony with the DTVC current injection. To take full advantage of multiphase current slew rate, the QZDPS is achieved with instant load estimation. Furthermore, to make DTVC compatible with QZDPS, the state transition logics for multiphase drive modulation are established with DTVC transient flags and QZDPS signal. It allows for a joint transient enhancement that pushes the load transient response of the MPVR to the physical boundary. According to experimental results, the proposed scheme improves the transient voltage deviation and response time by 38% and 75%, respectively. Along with the enhanced transient, the transient energy loss is reduced by 66%.

This article presents an optimal duty ratio assisted pulse frequency modulation control for very high frequency isolated class E dc–dc converter to achieve both continuous power flow and optimal switch timing. The continuous power flow significantly reduces output ripple of the converter, while the optimal switch timing guarantees consistent zero-voltage-switching (ZVS) and minimized reverse conduction loss. To pave the way for the proposed control, a resonant fitting model is established for deriving the optimal duty ratio and output power under dynamic switching frequency. The optimal duty ratio is calculated according to zero-crossing points of the switching node voltage ( v_ds ), and it aims to turn on the power switch once v_ds reaches zero. This ensures consistent ZVS while preventing reverse conduction of gallium nitride (GaN) high electron mobility transistor (HEMT) when the switching frequency changes. Furthermore, the proposed control is integrated with on/off modulation to extend load range of the converter. A 10–18 MHz prototype is built to verify effectiveness of the proposed control. Compared with conventional PFM control, the proposed control reduces the power loss by 35.9% at 40% load while maintains continuous power flow.

This paper presents a triple-mode average current control (TACC) strategy to achieve unity power factor and reduce the current stress for a boost PFC converter. The controller switches among different modes in each half-line cycle, and smooth transition is ensured by mapping of the operation region. By adaptive mode shifting, it reduces the current stress and current distortion caused by non-linear effects. With valley current shaping and comparisons, the TACC controller accordingly incorporates three control laws to adapt different modes. In discontinuous conduction mode (DCM), a variable on-time is calculated while the modulation is equivalent to PWM. In critical conduction mode (CRM), a constant on-time is derived, while the switching cycle is modified to regulate the current average value. For both DCM and CRM, the switching cycle is slightly extended to realize valley switching. Furthermore, with valley current shaping, the proposed controller reuses the CRM calculation to form continuous conduction mode (CCM) control law. To make the control laws compatible, normalized mapping and design rules are provided with respect to mode boundaries. This allows the TACC controller to automatically switch among different modes. Finally, experimental results prove the effectiveness of the controller in reducing the current stress and enlarging the preferable power range.

For very high frequency (VHF) class 2 inverter, conventional design method requires complex tuning for parameters. Without fully quantitative calculations, the tuning highly depends on experience that cannot achieve optimal design. In this paper, a target function design strategy is proposed based on quantitative harmonic weighting, which simplifies the design procedures and minimizes the switch voltage stress. Firstly, the target switch voltage with minimized peak value is derived by optimizing the harmonic weighting. With the result, the power switch is modeled as a voltage source to simplify the calculations, where the branch currents are solved to provided fully quantitative analysis. Based on the analysis, optimal features of switching node impedance are derived to achieve the target switch voltage. Additionally, basic constrains of the resonant tank are analyzed to reduce circling currents. Combining the optimal features and basic constrains of the resonant tank, the circuit parameters are calculated directly, which minimizes the switch voltage stress and improves power efficiency. Compared with conventional design, a 27.12MHz prototype demonstrates 10.2% reduction in average switch voltage stress and 7.2% improvement in average efficiency.