Desheng Zhang

For modular power supplies based on Intermediate Bus Architectures (IBAs), efficient current sharing is essential for system reliability and lifespan. To achieve compact and drop-compensated current sharing, this article proposes a cross-stage voltage-shifting (CSVS) strategy combined with a Ripple-frequency modulated transmission (RFMT) mechanism for modular IBA converters. A compensation model incorporating power loss estimation is developed, enabling the first-stage converter to compute the precise load voltage compensation value using the local measurements. With RFMT, the value is encoded into the intermediate bus ripple by modulating the PWM carrier frequency. The second-stage converters, operating under droop control, demodulate the ripple frequency, and shift their reference voltages accordingly, achieving CSVS-based voltage drop compensation under varying load conditions. Without centralized controllers, communication buses, or current-sharing lines, the proposed strategy offers high scalability while reducing the hardware complexity and cost. Experimental results confirm the effectiveness of the proposed method in accurate current sharing, drop compensation, and fast dynamic response.

Forsilicon carbide (SiC) MOSFET applications, it has been a constant challenge to address the trade-off among drain-source voltage slew rate (dv ${}_{\mathbf {ds}}$ /dt), drain-source voltage spike, and turn-off loss. The existing active gate drivers (AGDs) have not considered the influence of dynamically varying drain current, resulting in increased turn-off loss and voltage spike. To address this issue, this paper proposes a cross-cycle dynamic active gate driver (CDAGD) that features constant (dv ${}_{\mathbf {ds}}$ /dt) ${}_{\mathbf {max}}$ and spike under dynamic drain current. By deriving the quantitative relationship among the gate current,drain current, (dv ${}_{\mathbf {ds}}$ /dt) ${}_{\mathbf {max}}$ , and voltage spike, the optimal gate currents in different switching stages are determined. Furthermore, the CDAGD incorporates a cross-cycle gate current regulator (CCGCR) to generate the required gate currents in different stages, and a dynamic switching timing controller (DSTC) to locate the optimal timing of the stages. With the CDAGD providing the optimal gate current, the turn-off loss is minimized with reduced dv ${}_{\mathbf {ds}}$ /dt and spike.Fabricated in a $0.18\mu $ m BCD process, the CDAGD chip achieves a maximum reduction in turn-off loss of 72.2% and 37.9% compared with the conventional gate driver (CGD) and AGD under varying drain current. A 45.9% reduction in turn-off time is also achieved with the proposed gate driver.

Achieving low switching loss is critical for high-frequency gallium nitride (GaN)-based power converters due to the compact packaging and limited heat dissipation capacity of GaN devices. Focusing on minimizing the switching loss, this article proposes an adaptive three-stage gate driver (ATSGD) for GaN high electron mobility transistor (GaN HEMT). By providing a three-stage driving current within the Miller plateau (MP) stage, the proposed ATSGD can achieve a near-constant dV/dt, thus minimizing the switching loss under specific peak dV/dt constraints. Utilizing peak MP voltage tracking (PMPVT) and quick voltage tailing suppression (QVTS) techniques, the driver dynamically determines optimal switching timings for the three-stage driving currents in real time. Therefore, the extra losses caused by slow dV/dt start-up and voltage tailing effect are minimized under dynamic operation conditions. Fabricated in a $0.18~{\mu }$ m bipolar-CMOS-double-diffused metal oxide semiconductor (BCD) process, the proposed driver reduces the total switching loss by 36.4% under 400 V/15 A with a peak dV/dt of 45 V/ns, benefiting from a 46.1% reduction in slow dV/dt start-up loss and an 88.7% reduction in voltage tailing loss compared with conventional gate drivers.

This paper proposes a digital predictive peak current control (PPCC) strategy for superbuck converters. The proposed strategy incorporates a current predictor to calculate the output current and a peak current controller to calculate the required duty ratio for the next switching cycle. The duty ratio is precalculated ahead of a switching cycle, which creates a switching cycle for signal samplings and digital calculations. At the end of the next switching cycle, the output current peak value is regulated to match the reference value. The proposed strategy regulates the output current peak value to the reference value within two switching cycles. This increases the current loop bandwidth to π/T rad/s, which optimizes the transient performance. Moreover, a new damping parameter design method based on the damping ratio is given. Furthermore, a simplified version is proposed to facilitate digital realization. This version directly calculates the required duty ratio, which significantly reduces digital calculations. Finally, the experimental results demonstrate the effectiveness of the proposed control strategy in improving the transient performance of the superbuck converter.

The fast switching of gallium nitride high mobility transistor (GaN HEMT) results in high dv/dt and severe EMI issues, requiring a trade-off with the switching power loss. Three-stage gate drive (TSGD) can mitigate the conflict between switching speed and losses, but it is challenging to achieve minimal switching loss under the existing TSGD strategy due to the nonlinear parasitic capacitance of GaN HEMT. To address this issue, this paper proposes a minimal switching loss TSGD strategy based on a dynamic dv/dt switching model, which can achieve minimal switching loss. Firstly, based on the charge conservation principle, piecewise linear equivalent values for the parasitic capacitances of GaN HEMT are calculated. Based on the result, analytical expressions for the transient voltage and current in each switching stage are derived, which forms the dynamic dv/dt switching model and provides detailed analysis for the dv/dt nonlinearity. Furthermore, analytical expressions for switching loss during each stage are calculated, establishing the quantitative relationship between switching loss and drive conditions. By minimizing the total loss, the required driving currents and switching timings are determined. Finally, the MSL-TSGD strategy is proposed. Experimental results demonstrate that the proposed method reduces the turn-on loss by 18.6%, and reduces the turn-on delay by 29.3%.

This paper proposes a gallium nitride (GaN)-based very-high-frequency (VHF) resonant flyback converter with integrated magnetics, which utilizes the parasitic inductance and capacitance to reduce the passive components count and volume of the converter. Both the primary leakage inductance and the secondary leakage inductance of the transformer are utilized as the resonance inductor, while the parasitic capacitance of the power devices is utilized as the resonance capacitor. An analytical circuit model is proposed to determine the electrical parameters of the transformer so as to achieve zero voltage switching (ZVS) and zero current switching (ZCS). Furthermore, an air-core transformer was designed using the improved Wheeler’s formula, and finite element analyses were carried out to fine-tune the structure to achieve the accurate design of the electrical parameters. Finally, a 30 MHz, 15 W VHF resonant flyback converter prototype is built with an efficiency of 83.1% for the rated power.

With escalating dc bus voltage and power density for next-generation power supply, hybrid converters will suffer from high-voltage flying capacitors due to uneven voltage distribution. Besides, the increasing power density will not allow abundant decoupling capacitors to suppress transient voltage droop. To address these issues, this article proposes a hybrid converter, featuring uniform capacitor voltage and reconfigured inductive transient voltage clamping (TVC). The uniform capacitor voltage is ensured by an auto-sharing mechanism, which is proved in both time and frequency domains. Since the flying capacitor voltages are evenly alleviated, low-voltage capacitors are allowed to be used under 100 V dc bus. Furthermore, reconfigured inductive TVC scheme is developed to fully exploit the current slew-rate (SR) for multiphase operation. By transient detection and topology reconfiguration, the SR is boosted by 12 times during load transient, which can effectively suppress the transient voltage droop. An experimental prototype with 100 V input is built to verify the proposed topology and scheme. With the uniform voltage stress of 25 V, the volume of the flying capacitors is reduced by 84%. Moreover, with the reconfigured inductive TVC, the magnitude and recovery time of transient voltage droop are reduced by 85% and 41%, respectively.

This paper proposes a current balancing loop that is obtained using the threshold median adjustment (TMA-CBL) to achieve the accurate current balancing of an interleaved constant frequency hysteresis (CFH) buck converter. The CFH control is implemented with a frequency phase loop based on a threshold width adjustment (TWA-FPL). To ensure the loop’s stability and minimize the steady-state error, a multi-phase, coupled, small-signal model (MPC-SSM) is derived with a consideration of the coupling effect among the multiple phases. Furthermore, the current balancing error is analyzed in detail, with a consideration of the sensing resistance deviations in the loop. Finally, based on a 180 nm BCD process, a four-phase interleaved buck converter is fabricated to verify the effectiveness of the proposed TMA-CBL. The maximum current balancing error is within 0.68% when the sensing resistors are deviated by 5%.

In this paper, a sample voltage dead-beat control based on differentiative voltage prediction (DVP) and switching-cycle extension (SCE) is presented to achieve optimal transient response for DC-DC converters under discontinuous conduction mode (DCM) operation. Firstly, to improve load transient response, a DVP method is proposed to estimate the load. With the estimated load, the controller realizes load current feedforward and thus improves the transient response with a wide load range. Secondly, an SCE strategy is proposed to enlarge the output current range and output voltage slew rate, both of which have limited value under conventional digital pulse width modulation (DPWM). When the output current reaches the limited value, the proposed strategy increases the switching cycle to enlarge the current range without losing DCM operation. Finally, combining DVP with SCE, the converter not only achieves optimal response in large signal transients, but also doubles the load range in DCM operation.