Lei Ye

Topotactic phase‐transition (TPT) oxide memristors contain ordered 1D oxygen‐vacancy channels (OVCs) that enable anisotropic oxygen‐ion migration and reversible brownmillerite/perovskite transition, offering a materials platform for neuromorphic computing. However, the lack of spatially predefined oxygen‐ion migration sites in conventional TPT films promotes stochastic perovskite SrFeO ₃ conductive filament (CF) growth, compromising the response stability and state distinguishability required for reliable temporal signal processing. Here, a single‐component self‐assembled SrFeO _x memristor with alternating vertical and horizontal superlattice‐like OVC regions is reported. Structural characterization, density functional theory calculations, and kinetic Monte Carlo simulations indicate that this intrinsic self‐assembled architecture directs oxygen‐ion migration through vertical channels while horizontal regions restrict stray out‐of‐plane transport, promoting localized CF growth. The device combines forming‐free bipolar switching, an ON/OFF ratio of ∼4.4 × 10 ³ , low cycle‐to‐cycle (C2C) variation with CV(V _SET )/CV(V _RESET ) of 3.2%/0.6%, 16‐state retention over 10 ⁴ s, and endurance up to 10 ⁷ pulse cycles. Reproducible device‐to‐device (D2D) switching is obtained across 32 cells, with D2D CV(V _SET )/CV(V _RESET ) values of 10.1%/5.9%. Finally, the device's short‐term memory transforms temporal inputs into distinguishable states that a fixed linear readout decodes with 84.59% accuracy on a temporal classification task. This work highlights intrinsic OVC‐orientation engineering as a materials‐level strategy toward reliable single‐component TPT memristors.

Integrating logic control with adaptive synaptic learning at the device level is a key step toward high-performance computing-in-memory (CIM) hardware. However, the integration of logic-in-memory (LIM) and synaptic plasticity within a homogeneous device is hindered by the incompatibility between stable logic output and dynamic weight modulation. Here, we demonstrate a logic-synapse function-integrated device based on a two-dimensional (2D) floating-gate field-effect transistor (FGFET) with a coplanar dual-control-gate architecture. With two independent gate-coupling coefficients, the nominally symmetric design allows the gate-induced potential increments to superpose on the floating gate: cooperative inputs induce charge tunneling and write a new memory state, whereas antagonistic inputs approximately cancel the pulse-induced potential increment and latch the stored state. This rule directly implements LIM within a single device, enabling 14 reconfigurable Boolean logic operations with in situ nonvolatile output storage, a logic read margin of 104, and no external cascading for the demonstrated two-input logic functions. The same coupling framework further supports tunable synaptic plasticity, including lateral enhancement/inhibition and spatiotemporal competition/cooperation among multiple synaptic inputs. In particular, asynchronous competitive modulation modifies history-dependent conductance updates, improving the depression nonlinearity to 0.0833 while retaining a dynamic range of 22.82. These results establish an all-electrical device-level route for integrating logic control and neural weight adaptation in compact CIM hardware.

Optical computing offers a transformative approach for ultrafast, high‐throughput, and energy‐efficient information processing. However, most existing paradigms—whether on‐chip or free‐space—face a critical trade‐off: the pursuit of hardware reconfigurability and scalability through precise device structural design inherently compromises the unique properties that make light an exceptional medium for computation. Here, we propose a physics‐aware optical logic computing scheme that leverages the intrinsic nonlinearities of 2D MoS ₂ . By implementing a co‐encoding strategy that incorporates pump, probe, and control light features, our system realizes reconfigurable logic operations while maintaining the innate advantages of photonic computation. MoS ₂ flakes serve as multifunctional channels, in which light pulse power and delay are co‐encoded as input logic bits. These inputs activate a computational mechanism based on synergistic excited‐state absorption, generating measurable changes in relative transmittance that constitute the operation results. The co‐encoding principle grants exceptional reconfigurability, enabling the implementation of seven fundamental logic operations and signal demultiplexers. As a practical demonstration, we showcase all‐optical signal encryption and decryption with a per‐step operation speed of 5 ps and an operation energy consumption of 1.5 pJ. This physics‐aware optical approach provides a viable pathway to multifunctional optical computing hardware that reconciles reconfigurability with efficiency.

The von Neumann bottleneck in conventional computing architectures presents a significant challenge for data-intensive artificial intelligence applications. A promising approach involves designing specialized hardware with on-chip parameter tunability, which directly accelerates machine learning functions. This work demonstrates a continuously tunable mixed-kernel function physically realized within a van der Waals heterostructure. We designed and fabricated a MoTe ₂ /MoS ₂ type-Ⅱ vertical heterojunction phototransistor, which exhibits a non-monotonic, Gaussian-like optoelectronic response owing to its unique interlayer charge transfer mechanism. This intrinsic physical behavior directly maps to a mixed-kernel function combining Gaussian and Sigmoid characteristics. Furthermore, the hardware kernel can be continuously modulated by in-situ tuning of external optical stimuli. The mixed-kernel exhibited exceptional performance, achieving precision, accuracy, and area under the curve (AUC) values of 95.8%, 96%, and 0.9986, respectively, significantly outperforming conventional kernels. By successfully embedding a complex, adaptable mathematical function into the intrinsic physical properties of a single device, this work pioneers a novel pathway toward next-generation, energy-efficient intelligent systems with hardware-level adaptability.

The development of high-performance β-Ga2O3 electronics is critically hindered by the fundamental limitation of self-compensation in n-type doping, which severely suppresses free carrier concentrations. To explore the microscopic mechanism of this effect, we systematically investigate the four n-type dopants (Si, Sn, Ge, and Zr) in β-Ga2O3, combining first-principles calculations and experimental investigations. The calculation results show that the lower formation energies of SiGaVGa and SnGaVGa complexes compared to GeGaVGa and ZrGaVGa complexes lead to their higher concentrations and consequently stronger compensation in Si and Sn doping β-Ga2O3 under O-rich conditions. Oxygen annealing induces a severe compensation effect, as consistently validated by Hall effect and non-contact eddy current measurements. Beyond this universal mechanism, we further identify that the carrier compensation predominantly occurs near the surface, manifesting as a dramatic drop in near-surface carrier concentration and a sharp increase in contact resistivity in Sn-doped β-Ga2O3. Furthermore, photoluminescence spectra exhibit distinct green emission (∼2.5 eV), confirming the formation of the predicted deep-level defects SnGaVGa. This work reveals the microscopic compensation mechanism, providing vital theoretical and experimental insights for optimizing n-type β-Ga2O3 conductivity.

Conceptual overview of 2D materials-based flash memory: architectures, materials, and applications.

Federated learning is a communication collaborative learning architecture that protects personal privacy. Utilization of the ternary weight changes can efficiently reduce the communication workload and energy consumption of federated learning, which is beyond the realization of most single transistors. Here, we demonstrate a ternary state channel computing-in-memory transistor that can generate three conductivity states at a minimum ternary voltage of 5 mV for low-power computing and can distinguish the direction of weight changes for federated learning. The transistor has a relatively gentle conductivity state, where the current remains almost constant as the number of voltage pulses increases. Detection of this relatively gentle conductivity state can program the change of ternary weights in a single transistor. Based on these characteristics, the total communication bits were reduced by 83.3% in a custom federated learning task. The ternary state channel transistor shows potential as a basic hardware unit for ternary computing.