Zheng Li

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The proposed DCC loop provides precise and stable DCC, enabling robust time-domain gain modulation and mitigating phase perturbations typically associated with conventional VGA architectures. Implemented in 65-nm CMOS technology, the VGA consumes 4.9–103 mW from a 1-V supply, depending on the gain setting, and occupies a core area of $1150\times 280~\mu $ m. Measurements demonstrate a 30-dB continuous gain-control range with a 3-dB bandwidth from 24 to 30 GHz and a peak gain of 29.6 dB at 28 GHz. Across 24–29.7 GHz, the measured rms phase error ranges from 0.01° to 0.18° between the highest and lowest gain modes, validating the phase stability of the proposed approach. In addition, an output 1-dB (OP1dB) compression point of 12.5dBm is achieved, indicating robust large-signal performance. The proposed time-modulated VGA is well-suited for scalable millimeter-wave phased-array systems requiring wide-range gain control with minimal phase distortion.

This article presents a Ka-band phased-array multiple-input multiple-output (MIMO) receiver for sixth-generation (6G) wireless networks. A time-division (TD) MIMO architecture is combined with DP antenna array to support eight MIMO streams in the Ka band. The complex weights of each RF element in both polarization arrays are sequentially switched at the Nyquist rate to enable fast-stream switching for MIMO stream coexistence. The TD approach achieves full phased-array reuse and delivers high array gain and spatial selectivity for each stream at the expense of generating switching harmonics. To address this issue, a non-uniform time-hopping (TH) sequence is introduced in this article to spectrally spread the switching harmonics and mitigate the direct blocker folding. A proof-of-concept phased-array receiver is fabricated in 65-nm CMOS, integrating eight RF elements in a 7.2-mm² core area and consuming 335.2 mW. Combined with DP antennas, the phased-array receiver supports $4 \times 4$ TD-MIMO across both polarizations and achieves a maximum data rate of 38.4Gb/s using eight 800-MHz 64-QAM signals in over-the-air (OTA) measurements. Benefiting from the TD-MIMO architecture, the phased-array receiver achieves 0.078 mm² and 5.23 mW per element per stream. With the proposed non-uniform TH (NUTH) dithering, deep notches are generated at switching harmonics and 42.9-dB alias suppression is achieved. The proposed phased-array receiver also demonstrates a 34-dB improvement in blocker tolerance, maintaining –30-dB EVM_rms under a 0-dBc in-band blocker sweeping across –90° to 90° field of view (FoV) in MIMO OTA measurements.

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm² and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142–164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm², and it is implemented using a 65 nm CMOS process.

A tri-mode mixer supporting the 5G NR standards over 24.25--71GHz is presented. The harmonic-selection technique reduces the local oscillator (LO) frequency range and power consumption. Besides, the proposed multiphase LO rejects unwanted harmonics. Fabricated in a 65nm CMOS process, this work consumes 12-21mW power under a 1V supply. It presents more than 20dB rejections to the undesired harmonic components at all operation bands. The required LO frequency range is only 10GHz.

An 8-Element 28-GHz time-division MIMO beamformer supporting 4x4 MIMO is presented. A fast-switching phase shifter is utilized to realize Nyquist-rate beam switching to lossless receive multiple beams by reuse single RF signal path. A prototype fabricated in 65nm CMOS achieves 64-QAM 4x4 MIMO reception in OTA measurement using four 5G NR spatial data streams with 400MHz channel bandwidth.

A D-band (114--170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth with a 640-Gb/s data rate is proposed in this work. The design includes an 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) to improve bandwidth and linearity. The proposed TRX chipset achieves a 200Gb/s SISO data rate and a 640Gb/s MIMO data rate.

This work presents a D-band (110–170 GHz) CMOS transceiver (TRX) chipset that covers a 56-GHz (114–170 GHz) signal-chain bandwidth. Both the transmitter (TX) and the receiver (RX) operate as heterodyne architectures with external intermediate frequency (IF) and local oscillator (LO) signals. An eight-way low- Q power-combined power amplifier (PA), a two-way low- Q power-combined low-noise amplifier (LNA), wideband-impedance-transformation passive mixers, common-source-based cascaded distributed amplifiers (DAs), and a low-loss wideband chip-to-waveguide printed circuit board (PCB) transition are proposed with improved bandwidth and linearity to support high-order wideband quadrature amplitude modulation (QAM) signals. The TRX chipset was fabricated using a 65-nm CMOS process. The TX achieves a 13-dBm saturated output power at 130 GHz with 1150-mW dc power. The RX achieves a 12-dB noise figure (NF) with 550-mW dc power. The proposed TRX chipset achieves a data rate of 200 Gb/s by 32QAM in the single-input–single-output (SISO) over-the-air (OTA) measurement at 0.32 m. A data rate of 150 Gb/s by 16QAM is realized with 43-dBi antennas at 15 m. Additionally, a 640-Gb/s 4 $\times$ 4 OTA line-of-sight multiinput multioutput (LOS-MIMO) is demonstrated at 0.52 m.

This letter describes a fully synthesizable fractional- $N$ multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer- $N$ and fractional- $N$ operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.

This article presents a low-power 256-element $Ka$ -band CMOS phased-array receiver utilizing on-chip distributed radiation sensors for the low Earth orbit (LEO) small satellite communication system. Since the available solar cell area limits the power generation of the small LEO satellites, a distributed current-sharing common-gate (CG) low noise amplifier (LNA) and a voltage-tuning variable gain amplifier (VGA) are introduced to reduce power consumption. After utilizing the proposed technique, the power consumption of the beamformer is 2.95 mW/element. Moreover, the proposed voltage-tuning VGA is configured to utilize both upper and lower transistors for gain contributions to save power. The on-chip distributed radiation sensors are presented to eliminate the non-uniform radiation influence and realize 0.22-dB/Mrad gain degradation performance. The proposed receiver achieves $-$ 20-dBm single-element IIP3 with a 3.6-dB noise figure. The occupied on-chip area for a single element is only 0.24 mm $^2$ . DVB-S2X standard modulated signals of up to 256 amplitude and phase-shift keying (APSK) can be supported in the over-the-air (OTA) measurement. The receiver achieves $-$ 31.3-dB EVM and 24-Gb/s link speed under 1.5-GBaud dual-linear polarization signals. The measured 256-element beam pattern can cover radiated angle from $-$ 50 $^\circ$ to $+$ 50 $^\circ$ with lower than $-$ 9-dBc sidelobe level. Thanks to the proposed low-power distributed current-sharing CG LNA and on-chip radiation sensors, a low-power radiation-hardened phased-array receiver can be achieved for the small LEO satellites.