Yeongseok Jeong

The concept of negative capacitance (NC), originating from the intrinsic energy configuration of HZO ferroelectrics, has been predominantly utilized in logic transistors to achieve a steeper Id-Vg characteristic. Departing from these conventional approaches, we have developed an NC-NAND flash memory by integrating the NC phenomenon into the blocking oxide layer of conventional NAND flash memory. By leveraging the capacitance boosting effect of the NC-integrated blocking oxide (BO) layer, we can significantly enhance program (PGM) efficiency and lower the operating voltage of charge trap memory. In this work, we propose two combined approaches to improve the NC. First, we applied asymmetric tensile stress to the HZO layer through high-pressure annealing (HPA), thereby generating an internal electric field across the HZO layer. Additionally, we improved the polarization property of the HZO layer by employing a low-damage process during the deposition of the capping TiN electrode, minimizing interfacial damage to the HZO surface. Step-pulsed I-V measurement confirmed that the capacitance boosting effect of the NC blocking oxide with the low-damage process was improved by 16.7%, while the operating voltage was reduced by 1 V. Additionally, the NC-NAND flash memory with the low-damage process exhibited a significant higher ISPP slope characteristic.

This study proposes a self-rectifying ferroelectric tunnel junction (SR-FTJ) crosspoint array to satisfy the stringent size requirements of the Internet-of-Things devices. Each cell in the SR-FTJ crosspoint array consists of two SR-FTJs stacked vertically, resulting in ultrahigh density. The SR-FTJ crosspoint array can operate as: 1) ternary content-addressable memory (TCAM) or 2) binary content addressable memory (BCAM) or physically unclonable function (PUF) in the dual-mode operation. In the dual-mode operation, the amount of the current flowing through the SR-FTJs remains the same, resulting in a stable PUF response regardless of the BCAM data. The dual-mode operation of the SR-FTJ crosspoint array is experimentally verified by 4-in wafer-level demonstrations. HSPICE simulation results using the industrial-compatible 180-nm technology with the SR-FTJ model reflecting measured characteristics show that the SR-FTJ crosspoint array achieves the lowest search energy (2.05 fJ/search/bit) and the highest randomness (Hamming weight of 0.5000) among the previous content addressable memories (CAMs) and PUFs. In addition, the SR-FTJ crosspoint array reduces area by $>$ 84.2% compared to the previous structures that implement individual CAM and PUF.

Recently, hafnia-based ferroelectrics are currently being investigated as next-generation memory devices due to their excellent CMOS process compatibility and functionality. However, some of the ferroelectric devices commonly exhibit an imprint effect due to charged defects around the interfacial layer, which has negative impacts on the ferroelectric memory devices. However, it can be applied to various applications as long as the imprint field is carefully adjusted. In this work, we introduced a strategy to control the imprint field in bilayer capacitors by utilizing tantalum oxide (TaO) interfacial layers and various Zr contents in Hf_0.83Zr_0.17O₂ (HZO) films. The TaO layer (1 nm) was inserted into the bilayer capacitors to alter the imprint field's (positive or negative) direction. Whereas to control the imprint fields, we adjusted the Zr doping content (17%–83%) in the ferroelectric HZO films (8 nm). As the Zr content increased, reduced imprint fields were observed in those bilayer capacitors. In addition, it was found that a high imprint field (+2.43 MV/cm) was observed in Hf-rich films (Hf_0.83Zr_0.17O₂) due to the higher amount of oxygen vacancies. In addition, we examined those oxygen vacancies through x-ray photoelectron spectroscopy depth profile analysis by considering sub-oxide fractions in the tantalum, which further confirms the root cause of the imprint field variations in the bilayer capacitors. Our study will contribute to a deeper understanding of imprinted hafnia-based ferroelectrics and will provide an insight into devices that utilize the imprint effect.

Hafnia-based ferroelectric materials are recently drawing a significant attention for future electronic devices; however, there is a need to further enhance their functionality for practical applications. Especially, an imprinting effect has been regarded as a defect to be reduced in ferroelectrics; yet, it can be positively applied to various electronic devices with the functionality of self-rectifying behavior and threshold voltage adjustment. For the first time, we report a high imprinting effect in bilayer stack capacitors TiN/Hf $_{\text{0.5}}$ Zr $_{\text{0.5}}$ O $_{\text{2}}$ (HZO)/tantalum oxide (TaO)/TiN by employing an optimal TaO insertion layer. Furthermore, the imprinting effect was enhanced by adopting high-pressure annealing (HPA) process. X-ray photoelectron spectroscopy (XPS) depth profile analysis reveals that the origin of the imprint field is the tantalum suboxides (Ta $_{\text{2}}$ O $_{\text{5{\kern-0.2pt}-\textit{x}}}$ ) with doubly positively charged oxygen vacancies $^{^{^{^{}}}}$ (V $_{\text{o}}^{{++}}$ ). The imprint field increases with increasing HPA temperatures and achieved a high imprint field of 1.65 MV/cm at 600 $^{\circ}$ C. Moreover, endurance was observed up to 10 $^{\text{8}}$ cycles without a breakdown while maintaining the original coercive fields up to 10 $^{\text{5}}$ cycles. We also investigated how the TaO insertion layer with an imprint field influences the switching, interfacial, and ferroelectric properties. These findings on the imprinting effect provide a new strategy to improve the functionality of hafnia-based ferroelectric devices in the near future.