Chun-Yu Lin

This work presents a wideband high-speed transimpedance amplifier (TIA) with a co-designed bypass circuit and power clamp to address both power-supply noise and electrostatic discharge (ESD) reliability. Unlike conventional bypass designs that focus only on noise filtering, the proposed architecture explicitly considers current conduction under fast ESD transients. A multistage bypass network is integrated between the power rails (VDD-VSS) and co-optimized with a transient-triggered power clamp, providing a broadband low-impedance path for high-frequency noise while ensuring robust ESD discharge capability. Implemented in a CMOS process, the proposed TIA achieves a measured bandwidth (BW) of 27 GHz. Experimental results demonstrate a human body model (HBM) robustness of up to 7 kV, a transmission line pulse (TLP) secondary breakdown current (I_t2) of 3.86 A, and a very-fast TLP (VF-TLP) I_t2 of 11.66 A. These results verify that the proposed bypass–clamp co-design effectively enhances reliability without degrading high-speed performance.

Although conventional power-rail electrostatic discharge (ESD) clamp circuits are essential for ESD protection, they are prone to false triggering during fast power-on events. This phenomenon can lead to excessive current consumption and potential reliability concerns. Furthermore, leakage current exacerbates these issues by increasing static power dissipation and compromising long-term stability. To address these challenges, this study proposes a power-rail ESD clamp circuit that is tolerant to 2xVDD. This circuit incorporates a dual detection mechanism, integrating time detection and voltage detection to prevent false triggering during fast power-on events. Additionally, N-well and deep N-well isolation techniques are employed to effectively suppress parasitic NPN structures, thereby reducing leakage current and enhancing ESD robustness. The proposed circuit is implemented using the TSMC 180 nm CMOS process. Measurement results indicate that at room temperature, the leakage current is maintained at the level of nanoampere, and the circuit achieves a human-body-model (HBM) ESD robustness exceeding 8 kV. Even under 2xVDD operation, the design maintains ultra-low leakage current and exhibits excellent ESD protection capabilities, thereby improving energy efficiency and long-term reliability.

Electrostatic discharge (ESD) remains a critical reliability issue in CMOS technologies. This paper reviews the fundamentals of ESD phenomena and introduces representative on-chip protection structures. To address the shrinking margin between supply voltage and gate oxide breakdown, the concept of the ESD design window is introduced as a fundamental constraint for selecting and sizing protection devices. The inherent trade-off between ESD robustness and latch-up immunity is also addressed, highlighting strategies to prevent accidental activation during normal operation. It is further indicated that effective ESD protection is a comprehensive chip-level requirement that extends beyond I/O pads to include robust power-rail clamping and internal protection. Diode-based protection, SCR-based devices, and MOS clamps are discussed with emphasis on their operating principles, discharge paths, and design trade-offs. The coordination between I/O protection and power-rail clamps is highlighted as an essential requirement for forming complete discharge paths during ESD events. In addition to presenting the key device and circuit concepts, this paper also clarifies how these structures are typically integrated into practical chip designs, providing readers with both intuitive understanding and circuit-level design guidelines that can be directly applied in design practice. Finally, future challenges are outlined, including the impact of advanced technology scaling, three-dimensional integration, chiplet-based architectures, and increasingly stringent system-level standards. By combining fundamental insights with circuit-level perspectives, this paper aims to serve as a clear and accessible tutorial foundation, helping circuit designers and researchers build a comprehensive understanding of ESD protection for modern and future semiconductor technologies, and supporting continued progress in reliable electronic system design.

A cost-efficient electrostatic discharge (ESD) protection solution for the gate-to-source terminal of GaN-based power high-electron-mobility transistors (HEMTs) is proposed. High ESD robustness of the GaN-based power HEMT has been successfully achieved by co-packaging a transient voltage suppressor (TVS) inside the package together, while a 32.6% reduction in cost as comparing to that with on-die bidirectional ESD protection circuit can be gained. Human-body-model (HBM) ESD level exceeding ±7 kV has been verified, indicating the effectiveness of the proposed solution for protecting the gate-to-source terminal of GaN-based power HEMT.

The increasing complexity and integration of high-speed and high-frequency electronic systems have heightened the need for robust on-chip electrostatic discharge (ESD) protection to meet stringent reliability requirements. However, integrating ESD protection into these systems is challenging, as conventional protection devices introduce parasitic capacitance that degrades signal integrity, disrupts impedance matching, and limits bandwidth. This article provides a comprehensive overview of modern on-chip ESD protection techniques tailored for high-speed and high-frequency applications. The discussion covers a range of strategies, including diode-based devices, silicon-controlled rectifier (SCR)-based structures, stacked configurations, and the use of passive elements such as resistors, inductors, and T-coil. These approaches aim to achieve reliable ESD protection while maintaining signal performance across wide frequency bands. In addition, this review highlights recent advancements in low-capacitance (low- ${C}\text {)}$ ESD structures and integration techniques that leverage parasitic components of protection circuits to complement signal path design. As electronic systems evolve toward higher frequencies, faster speeds, and greater integration, the development of compact, high-efficiency ESD protection circuits will remain a key enabler for future high-performance designs.

A compact electrostatic discharge (ESD) protection circuit using silicon-controlled rectifiers (SCRs) for radio frequency (RF) $I$ /O interfaces is proposed and implemented in the TSMC 0.18- $\mu $ m CMOS process. The design ensures robust ESD protection by enabling discharge through multiple paths between the $I$ /O pins and power rails. To mitigate the parasitic capacitance introduced by the SCRs, an inductor is integrated for compensation. As a result, the proposed circuit achieves comprehensive ESD protection while preserving high signal integrity and minimizing chip area, making it a highly efficient solution for high-frequency applications.

Advanced CMOS chips are often integrated with multiple power domains to fulfill sophisticated functionalities, which complicates cross-power domain electrostatic discharge (ESD) protection. In this work, a novel silicon-controlled rectifier (SCR) device, named nMOS-triggered dual-power SCR (NMT_DP_SCR), featuring up to 12 discharge paths for ESD protection, is proposed and demonstrated in a 0.18- $\mu $ m CMOS process. The NMT_DP_SCR, with embedded multiple discharge paths, is optimized for ESD protection in advanced CMOS technologies with isolated power domains. Among the 12 discharge paths, the most vulnerable path achieves a transmission line pulse (TLP) second breakdown current ( ${I} _{\text {t}{2}}$ ) of 3.78 A and a human-body model (HBM) ESD robustness of 4500 V. The full-chip ESD protection capability of the NMT_DP_SCR device is further verified through integration with a level shifter across two separate power domains. A record-high figure of merit (FoM), evaluated as the most vulnerable discharge current times the number of the discharge paths per unit area, is achieved by the proposed NMT_DP_SCR device.

ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18- $\mu $ m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.