Xin Xu

This paper investigates a 60 GHz low-power broadband low noise amplifier (LNA) with variable gain control. To prove the concept, the circuit is implemented in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology. It supports broadband operation at 60 GHz achieved by gain peaking (gain distribution) technique. By tuning some key matching networks of the amplifier, the peak gain of each stage was distributed to different frequencies resulting in an overall broadband frequency response. The circuit consists of three cascaded cascode amplifier stages. Matching networks were optimized regarding bandwidth and noise figure. The transistor back-gate was used for LNA designs to switch the circuit to low-power standby mode. This avoids the problems of front-gate based switching regarding voltage breakdown and circuit stability. Additionally, simultaneous realization of variable gain control at such high frequencies was achieved via the back-gate. Compared to the front-gate based, the back-gate based variable gain control can deliver a continuous fine-tuning of the gain while requiring less accuracy or resolution of the control voltage. In the measurement, The gain was successfully tuned from 20 dB down to −25 dB via the back-gate. At a DC power of 8.1mW from a nominal supply of 1V, the LNA provides a peak gain of 20 dB, a bandwidth of 18.5 GHz, and a minimum noise figure of 3.3 dB. When biased at a reduced DC supply of 0.4V, the presented circuit consumes only 2.5mW of DC power, and still provides a power gain of 10 dB and a minimum noise figure of around 4.5 dB. By switching to standby mode, the LNA consumes 850 µW of DC power at the nominal supply and 240 µW at the reduced supply. The LNA compares well against previously reported designs by showing the lowest noise figure with competitive gain, bandwidth and DC power. To the authors’ knowledge, this is the first 60 GHz LNA featuring joined variable gain control and switching capability via solely back-gate biasing.

This letter presents a feasibility study for a 62 GHz power amplifier (PA) in a 22 nm CMOS technology with integrated data modulation via the back-gate. The proposed PA consists of two pseudo-differential cascode stages, and provides a peak gain of 23.3 dB, a Psat of 13.6 dBm and a peak PAE of 28.3%. The PA consumes 96 mW from a 2 V VDD at its saturation. Thanks to the transistor back-gate, the PA can be dynamically switched on and off by increasing the threshold voltage through the back-gate. This avoids AC ground, gain and stability problems caused by conventional front-gate switching. In off-mode it draws 2.5% of its peak DC power. Rise-and fall-times of 1 ns were measured. The possibility of back-gate based modulation was experimentally demonstrated, showing that the PA can be used as a single device transmitter. Compared to previously reported works the PA shows one of the highest PAE and excellent linearity. To the best knowledge of the authors, this is the first investigation of a 60 GHz PA with data modulation via the back-gate.

This paper presents the authors’ experience in using the Dynamical Mode Decomposition (DMD) for estimating electromechanical oscillation modes from real synchrophasor data from the Dominion Energy system. To gain insight into the effectiveness of this approach, the results obtained from DMD on ambient data are compared against frequency domain approaches. Furthermore, the challenges in using this method are highlighted. The comparison shows that DMD is suitable for mode estimation from ambient data and should be further investigated for real world deployment within wide-area monitoring systems.