Xingshuai Zou
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Xingshuai Zou has a total of 20 co-authors. Here are the top co-authors by number of shared publications:
- Jiaxin Liu
University of Electronic Science and Technology of China
4 shared publications - Shiheng Yang
School of Electronic Science and Engineering, University of Electronic Science and Technology of China (UESTC), Chengdu, China
3 shared publications - Hongshuai Zhang
School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China
2 shared publications Jialin Hu
School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China
2 shared publications- Xiangyu Mao
School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu, China
2 shared publications - Biao Wang
Formula Microelectronics, Shanghai, China
1 shared publication
Latest Publications
- 13 February 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 72 (10) , 5399-5408
A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling
The zoom ADC can achieve high resolution with low power by a coarse-fine architecture, but its bandwidth is very limited due to oversampling during the fine $\Delta\Sigma$ conversion. This paper presents a single-sampling incremental zoom ADC. It addresses the fundamental bandwidth limitation by obviating oversampling while still retaining the merit of noise shaping. It also realizes the efficient three-step conversion with a highly hardware-reused architecture. A prototype ADC is implemented in 28 nm CMOS process. Operating under 5 MS/s sampling rate and 0.9-/1.8-V dual power supplies, it measures 89.5 dB signal-to-noise-and-distortion ratio (SNDR) and 93.4 dB dynamic range (DR) with 2.5 MHz bandwidth while consuming 2.36 mW power and occupying 0.19 mm2 area. Overall, this work achieves the competitive SNDR-based Schreier FoM of 179.7 dB and DR-based Schreier FoM of 183.6 dB.
- 13 February 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 72 (10) , 5399-5408
A 5-MS/s 93.4-dB-DR Three-Step Incremental Zoom ADC With Single Sampling
The zoom ADC can achieve high resolution with low power by a coarse-fine architecture, but its bandwidth is very limited due to oversampling during the fine $\Delta\Sigma$ conversion. This paper presents a single-sampling incremental zoom ADC. It addresses the fundamental bandwidth limitation by obviating oversampling while still retaining the merit of noise shaping. It also realizes the efficient three-step conversion with a highly hardware-reused architecture. A prototype ADC is implemented in 28 nm CMOS process. Operating under 5 MS/s sampling rate and 0.9-/1.8-V dual power supplies, it measures 89.5 dB signal-to-noise-and-distortion ratio (SNDR) and 93.4 dB dynamic range (DR) with 2.5 MHz bandwidth while consuming 2.36 mW power and occupying 0.19 mm2 area. Overall, this work achieves the competitive SNDR-based Schreier FoM of 179.7 dB and DR-based Schreier FoM of 183.6 dB.
- Open Access
- 12 February 2023
- Published by Wiley
Fully Passive Noise-Shaping SAR ADC Realizing 2X Passive Gain Without Capacitor Stacking
The fully passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) are simple, OTA-free and scaling friendly. Previous passive NS-SAR ADCs rely on the multi-path-input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high-order systems. This work proposes a new fully passive NS-SAR technique, it can realize 2× gain with a simple structure, leading to the reduced comparator power and less parasitics. This technique is also easy to extend to high-order NS-SAR ADCs.
- 12 February 2023
- Published by Wiley
Open AccessFully Passive Noise-Shaping SAR ADC Realizing 2X Passive Gain Without Capacitor Stacking
The fully passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converters (ADCs) are simple, OTA-free and scaling friendly. Previous passive NS-SAR ADCs rely on the multi-path-input comparator or capacitors stacking to realize the passive gain for compensating the signal attenuation during passive integration. However, the former causes high comparator power consumption, and the latter suffers from additional signal attenuation due to the parasitics and is hard to extend to high-order systems. This work proposes a new fully passive NS-SAR technique, it can realize 2× gain with a simple structure, leading to the reduced comparator power and less parasitics. This technique is also easy to extend to high-order NS-SAR ADCs.