HyunJoon Jeong

Emerging transistors lack the statistical compact models needed to evaluate the yield of integrated circuits. To address this, we propose a novel framework combining a variational autoencoder (VAE) and an artificial neural network (ANN). Through the VAE method, a unique set of sources of unexpected process variations in I–V curves can be extracted. Furthermore, the latent vectors serve as inputs to an ANN-based compact model, which enables efficient Monte Carlo (MC) simulations. The proposed ANN-based statistical compact model was experimentally validated using fabricated roll-to-roll (R2R) printed single-walled carbon nanotube thin-film transistors (SWCNT TFTs). The model achieved greater than 98% fit accuracy on measured devices and greater than 90% similarity in key figures of merit (FoMs) in device-level statistical simulations. Our proposed model was implemented in Verilog-A and utilized in SPICE simulations. Our experimental results highlight the framework’s adaptability and efficiency in handling unknown process variations. This data-driven approach for assessing the yield of emerging transistors has the potential to become a cornerstone of future design technology co-optimization (DTCO).

To overcome the difficulty in model parameter extraction and the narrow model coverage of physics-based compact models, artificial neural network-based compact models (ANN CM) have been developed. However, the ANN CM lacks physical consistency and sub-models for circuit simulations. In this work, we propose an innovative hybrid compact model that uses a physics-based compact model as a basis with accurate fitting capability over a wide range using two neural networks (NN). First, a bidirectional physics-based compact model generator neural network (PMG-NN) can automatically extract model parameter sets for both the drain current and gate capacitance within a few minutes. Second, a deep global correction neural network (DGC-NN) corrects the electrical inconsistencies caused by process variations to solve the narrow model coverage issues. The hybrid compact model (Hybrid CM) using DGC-NN can predict I_ds, C_gg, C_gd, and C_gs of TCAD-simulated 3 nm nanosheet FETs (NSFETs) with greater than 98.5% accuracy. The hybrid compact model was implemented using Verilog-A and validated through the Gummel symmetry test and SPICE simulations. This new type of compact model has the potential to be the best solution for efficient process optimization and accurate SPICE simulation in real-world applications.

Neural network (NN)-based compact modeling methodologies are gaining attention due to the challenges of device complexity, narrow model coverage, and SPICE simulation speed in advanced semiconductor technology nodes. As device complexity increases, the number of process and structural variables also increases, which significantly increases the amount of technology computer-aided design (TCAD) simulation data required for NN-based compact modeling. This study proposes a multi-fidelity model and active learning approach to predict global and local variations of nanosheet FETs (NSFETs) with less than 1.5% error, significantly reducing the number of required TCAD simulations by more than half compared with conventional modeling techniques. In addition, the simplified NN model with a smaller training dataset significantly reduces the SPICE simulation time.

In this study, a novel dual- k spacer ferroelectric field-effect transistor (FeFET) structure is proposed. By adopting the dual- k spacer for the first time in FeFET, the target memory window (MW) of 0.5 V is achievable at a write voltage of 5 V. The write voltage shows a 2.0-V reduction from 7 V for the low- k spacer FeFET (L-FeFET) and a 1.0-V reduction from 6 V for the high- k spacer FeFET (H-FeFET). The write power of the proposed FeFET was 25.9% lower than that of the low- k FeFET and H-FeFET. These improvements significantly expand the Pareto front and mitigate the effects of trapped charge. The dual- k spacer FeFET structure is a promising candidate for low-voltage and low-power operations.

Optimizing the nonlinear electrical characteristics of sub-3-nm devices requires considerable trial and error. However, due to the complexity of physics and secondary effects, technology computer-aided design (TCAD) simulations are time-consuming. Even with a combination of TCAD and a suitable design of experiments (DOEs), comprehensive exploration of the design space using TCAD is a challenging task. In this study, we propose a device optimization framework that can dramatically reduce the number of TCAD simulations while identifying the optimal device structure. The framework we propose consists of an artificial neural network (ANN)-based objective function derived from a dataset generated by weighted Sobol sampling, a multiobjective Bayesian optimization (MOBO) model for device optimization, and an ANN-based compact model for circuit simulation. The framework produced a device structure that showed a 51.5% performance improvement compared to the best device performance found from individual TCAD simulations of 128 structures. In contrast, the manual determination of a device achieving similar results required more than 2048 TCAD simulations.

The artificial neural network (ANN)-based compact model has significant advantages over physics-based standard compact models such as BSIM-CMG because it can achieve higher accuracy over a wide range of geometric parameters. This makes it particularly suitable for design space exploration and optimization. However, the ANN-based compact model using only one set of model parameters (global-ANN) requires larger model sizes to achieve wider coverage and higher accuracy in order to capture the unpredictable nonlinearities of emerging devices. This results in reduced simulation speed and a trade-off between simulation accuracy, model coverage, and simulation speed makes it difficult to utilize ANN-based compact models in a variety of ways. To solve this problem, we propose the first ANN-based compact modeling flow using a binning method (binning-ANN) and we address the training requirements and data sparsity issues that may occur due to the binning method in ANNs. In addition, we develop a bin size optimization guideline for the binning-ANN. As a result, the binning-ANN not only has higher accuracy, but also much better expandability than existing methods.

In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.