Ajay Kumar

This work presents a numerical analysis of a highly efficient NiO/PCBM interface engineered lead-free CsSn _0.5 Ge _0.5 I ₃ -based perovskite–silicon tandem solar cell using SCAPS-1D. With the optimization of the NiO/PCBM interface, the single-junction perovskite cell achieves an efficiency of 21.3%, with a V _oc of 0.99 V, J _sc of 26.36 mA/cm², and FF of 81.7%, at a 0.6 μm absorber thickness. When the perovskite top cell is combined with a c-Si bottom cell in a tandem structure, the device achieves a PCE of 30.91%, with a V _oc of 1.79 V, J _sc of 20.24 mA/cm², and FF of 85.34%. Further, the perovskite thickness and interface defect density have also been optimized to improve the device efficiency. The NiO/PCBM layers enhanced carrier transport and reduced recombination, resulting in increased quantum efficiency (∼95%) and stability. This performance surpasses previous Spiro-OMeTAD/PCBM-based tandem cells and only CsSn _0.5 Ge _0.5 I ₃ -based tandem solar cells which validates the CsSn _0.5 Ge _0.5 I ₃ /NiO/PCBM/c-Si tandem devices as a practical and long-term solution for advanced photovoltaic applications.

Perovskite solar cells (PSCs) display extraordinary power conversion efficiencies (PCEs); as the third-generation thin film solar cell, it showcases remarkable PCE nearing 25%, surpassing other solar cell types such as C-Si (23%), CdTe (22%), and CIGS (23–24%). Nevertheless, challenges like instability, lead toxicity, and interfacial recombination obstruct their market introduction. This study utilized a numerical simulation method with SCAPS-1D to evaluate the efficacy of chalcogenide-based perovskite solar cells featuring a structure of FTO/CdS/BaZrS ₃ /HTL/Ir. Four-hole transport layers (HTLs)-Cu ₂ O, CuSCN, P3HT, and PEDOT: PSS-were evaluated to examine the way they affect the performance of the device. The thickness of the absorber and the bulk densities in the HTL were optimized for peak efficiency. Of all the configurations, devices based on PEDOT: PSS reached the highest PCE of 23.63% while the other devices based on P3HT, CuSCN, and Cu ₂ O reached the PCE of 12.21%, 12.25%, and 14.14% respectively. The other photovoltaic parameters for the best device having PEDOT: PSS as HTL were an open-circuit voltage (Voc) of 1.261691 (V), short-circuit current density (Jsc) of 22.42723734 mA/cm ² , and a Fill Factor of 83.53% due to advantageous energy alignment and diminished recombination losses. This study highlights the significance of selecting HTL and optimize absorbers in order to achieve effective, environmentally friendly PSCs.

In this letter, a paper-based flexible strain gauge has been proposed using standard office paper and everyday graphite pencil. Detailed analysis and characterization of several design parameters and sensor configurations have been investigated experimentally, such as the width and length of the electrodes and pencil graphite content. In addition, sensor topologies, such as the Wheatstone bridge configuration, have been investigated to achieve a highly sensitive strain gauge device. A full Wheatstone bridge configuration has been chosen based on the optimized design parameters. The fabricated structure demonstrated promising results with great sensitivity, high stability, and a wide uniform range from maximum tension to maximum compression. The proposed full Wheatstone device allows environmental compensation and exhibits a very high gauge factor of 40.2 for tensile strain and 34.4 for compressive strain for a deflection range of −30 to 30 mm. The proposed full, pencil-drawn Wheatstone bridge configuration is cost-effective and easy to fabricate with high sensitivity at 130 mV/V, spanning the entire range of the device. This enables compatibility with standard electronic readout platforms, including microcontrollers, for biomedical sensing, machine–human interfaces, and strain-sensing applications.

This work presents an analysis of the performance of Gallium Nitride Truncated Fin FinFETs (GaN-TF-FinFET) and compares them with conventional (C) FinFET, TF-FinFET, and silicon-on-insulator (SOI) TF-FinFET in analog and RF applications by using advanced simulation techniques at the 7 nm technology node and a low supply voltage (V_DS = 0.3 V). This work evaluates key analog and high-frequency performance metrics of the GaN-TF-FinFET. The results show a 60% increase in drain current, leading to improved transconductance and switching speed. Additionally, the subthreshold slope is reduced to 34 mV/decade, representing a 93.74% improvement compared to the C-FinFET. Furthermore, the GaN-TF-FinFET demonstrates the lowest DIBL and the highest electron mobility. Parameters such as stray capacitance, f_T, f_MAX, GFP, TFP, and GTFP are superior in GaN-TF-FinFET, highlighting its high-frequency performance. Our findings demonstrate significant improvements in device efficiency and signal integrity, positioning GaN-TF-FinFET as a promising device for next-generation high-frequency applications.