Raymond H. Yang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Raymond H. Yang has a total of 6 co-authors. Here are the top co-authors by number of shared publications:
- Alexander Orzechowski1 shared publication
- Brett H. Meyer
McGill University
1 shared publication - Hao Shu1 shared publication
- Loren Lugosch
Department of Electrical and Computer Engineering McGill university
1 shared publication - Wei Li1 shared publication
- Yaqing Xia
Cannan Inc., Beijing, China
1 shared publication
Latest Publications
- 15 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test
- Vol. 41 (6) , 28-35
An Open-Source 12-bit 10-kS/s Incremental ADC in 130-nm CMOS
Recent advancements in open-source silicon have led to more affordable and accessible silicon design and fabrication. This paper presents a 12-bit 10-kS/s incremental analog-to-digital converter (ADC) in SkyWater’s 130 nm CMOS technology, designed using open-source design tools and process design kit (PDK). A second-order delta-sigma (ΔΣ) modulator with 512 times oversampling was used with a 1-bit comparator for simplified circuit implementation and linearity. The ADC achieves a peak SNDR of 57 dB and peak SNR of 67 dB, with 9.1 effective bits and 1.53 mW total power consumption on silicon. Silicon performance was compared with limited simulation performance numbers obtained using open-source circuit simulators.
- 15 August 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test
- Vol. 41 (6) , 28-35
An Open-Source 12-bit 10-kS/s Incremental ADC in 130-nm CMOS
Recent advancements in open-source silicon have led to more affordable and accessible silicon design and fabrication. This paper presents a 12-bit 10-kS/s incremental analog-to-digital converter (ADC) in SkyWater’s 130 nm CMOS technology, designed using open-source design tools and process design kit (PDK). A second-order delta-sigma (ΔΣ) modulator with 512 times oversampling was used with a 1-bit comparator for simplified circuit implementation and linearity. The ADC achieves a peak SNDR of 57 dB and peak SNR of 67 dB, with 9.1 effective bits and 1.53 mW total power consumption on silicon. Silicon performance was compared with limited simulation performance numbers obtained using open-source circuit simulators.
- Open Access
- 23 April 2023
- Published by Elsevier in Energy and AI
- Vol. 14
A data-driven framework for medium-term electric vehicle charging demand forecasting
- 23 April 2023
- Published by Elsevier in Energy and AI
- Vol. 14
Open AccessA data-driven framework for medium-term electric vehicle charging demand forecasting