Jiaan Zhou
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Jiaan Zhou has a total of 37 co-authors. Here are the top co-authors by number of shared publications:
Bohan Guo
School of Nano‐Tech and Nano‐Bionics University of Science and Technology of China Hefei People's Republic of China
4 shared publicationsBosen Liu
Nanofabrication Facility Suzhou Institute of Nano‐Tech and Nano‐Bionics Chinese Academy of Sciences Suzhou Jiangsu People's Republic of China
4 shared publicationsRunxian Xing
School of Nano‐Tech and Nano‐Bionics University of Science and Technology of China Hefei People's Republic of China
4 shared publicationsBaoshun Zhang
School of Nano‐Tech and Nano‐Bionics University of Science and Technology of China Hefei People's Republic of China
3 shared publicationsGuohao Yu
School of Nano‐Tech and Nano‐Bionics University of Science and Technology of China Hefei People's Republic of China
3 shared publicationsYu Li
School of Nano‐Tech and Nano‐Bionics University of Science and Technology of China Hefei People's Republic of China
3 shared publications
Latest Publications
- 8 August 2026
- Published by Wiley in Physica Status Solidi (RRL) – Rapid Research Letters
- Vol. 20 (8) , e70230
Hydrogen‐Plasma‐Enabled Ultrafast p‐GaN/AlGaN/GaN Hybrid Anode Diode for Visible‐Blind Near‐Ultraviolet Photodetection
We demonstrate a visible‐blind near‐ultraviolet (near‐UV) photodetector based on a hydrogen‐plasma‐treated two‐terminal p‐GaN‐gated hybrid‐anode diode. In the dark, the p‐GaN optical gate depletes the AlGaN/GaN two‐dimensional electron gas (2DEG), yielding a dark current of 6.82 × 10 −9 mA/mm (normalized to gate width). Under 365‐nm illumination, 2DEG recovery increases the photocurrent to 12.99 mA/mm and yields a 365‐nm responsivity of 7.7 × 10 3 A/W. Enabled by an etch‐free gate‐definition HPT process that mitigates trap‐assisted effects, the device exhibits rise and fall times of 22.96 and 167.87 μs, respectively. These results indicate that the HPT‐enabled HAD combines low dark current, high responsivity, and microsecond‐scale response for GaN‐based near‐UV photodetection.
- 8 August 2026
- Published by Wiley in Physica Status Solidi (RRL) – Rapid Research Letters
- Vol. 20 (8) , e70230
Hydrogen‐Plasma‐Enabled Ultrafast p‐GaN/AlGaN/GaN Hybrid Anode Diode for Visible‐Blind Near‐Ultraviolet Photodetection
We demonstrate a visible‐blind near‐ultraviolet (near‐UV) photodetector based on a hydrogen‐plasma‐treated two‐terminal p‐GaN‐gated hybrid‐anode diode. In the dark, the p‐GaN optical gate depletes the AlGaN/GaN two‐dimensional electron gas (2DEG), yielding a dark current of 6.82 × 10 −9 mA/mm (normalized to gate width). Under 365‐nm illumination, 2DEG recovery increases the photocurrent to 12.99 mA/mm and yields a 365‐nm responsivity of 7.7 × 10 3 A/W. Enabled by an etch‐free gate‐definition HPT process that mitigates trap‐assisted effects, the device exhibits rise and fall times of 22.96 and 167.87 μs, respectively. These results indicate that the HPT‐enabled HAD combines low dark current, high responsivity, and microsecond‐scale response for GaN‐based near‐UV photodetection.
- 22 December 2024
- Published by Wiley in Physica Status Solidi (a)
- Vol. 222 (8)
Analysis and Manufacturing of GaN Trench‐Gate MOSFETs with Thick Bottom Dielectric
Herein, A high‐performance GaN vertical trench‐gate metal‐oxide‐semiconductor field‐effect transistor (MOSFET (UMOSFET)) with polyimide (PI) as the thick‐bottom dielectric (TBD) is numerically studied and experimentally demonstrated. It is demonstrated that the inclusion of TBD can effectively suppress the peak electric field at the bottom corner of the gate trench and prevent premature breakdown of the devices. According to the technology computer‐aided design simulation results, the UMOSFETs with larger TBD thickness (tTBD) exhibit enhanced breakdown voltage (VBR) with minor expense of specific on‐resistance (Ron,sp) and a significantly improved Baliga's figure of merit. Compared with the conventional GaN UMOSFETs without TBD, the fabricated GaN UMOSFETs with 500 nm‐thick PI as TBD feature a remarkable 1.5 times enhancement in breakdown voltage VBR to 407 V, highlighting the feasibility and potential of the PI‐TBD to propel the further development of GaN vertical devices toward the inherent material and device ultimate.
- 22 December 2024
- Published by Wiley in Physica Status Solidi (a)
- Vol. 222 (8)
Analysis and Manufacturing of GaN Trench‐Gate MOSFETs with Thick Bottom Dielectric
Herein, A high‐performance GaN vertical trench‐gate metal‐oxide‐semiconductor field‐effect transistor (MOSFET (UMOSFET)) with polyimide (PI) as the thick‐bottom dielectric (TBD) is numerically studied and experimentally demonstrated. It is demonstrated that the inclusion of TBD can effectively suppress the peak electric field at the bottom corner of the gate trench and prevent premature breakdown of the devices. According to the technology computer‐aided design simulation results, the UMOSFETs with larger TBD thickness (tTBD) exhibit enhanced breakdown voltage (VBR) with minor expense of specific on‐resistance (Ron,sp) and a significantly improved Baliga's figure of merit. Compared with the conventional GaN UMOSFETs without TBD, the fabricated GaN UMOSFETs with 500 nm‐thick PI as TBD feature a remarkable 1.5 times enhancement in breakdown voltage VBR to 407 V, highlighting the feasibility and potential of the PI‐TBD to propel the further development of GaN vertical devices toward the inherent material and device ultimate.
- 12 June 2024
- Published by Wiley in Physica Status Solidi (RRL) – Rapid Research Letters
- Vol. 18 (11)
Annealing Process on Metal–Oxide–Semiconductor Channel Properties for Quasivertical GaN‐on‐Sapphire Trench Metal–Oxide–Semiconductor Field‐Effect Transistor
Quasivertical gallium nitride trench‐gate metal–oxide–semiconductor field‐effect transistors with different etch radio frequency power and the impact of the order of annealing process in tetramethylammonium hydroxide wet treatment have been fabricated and studied. The high‐power device has a threshold voltage of 5.3 V and a maximum saturation current density of 552 A cm−2, whereas the low‐power device has a threshold voltage of 4.5 V and a maximum saturation current density of 650 A cm−2. However, the low‐power device has more severe off‐state leakage due to more fixed charges and defects on the device surface. Furthermore, the annealing process serves as an additional step before wet treatment. Scanning electron mircoscope image indicates that annealing at high temperatures prior to etching can eliminate surface oxide and redistribute surface imperfections, resulting in a smoother sidewall morphology. The relationship between temperature and mobility confirms the impact of the crystal surface feature on device performance.
- 12 June 2024
- Published by Wiley in Physica Status Solidi (RRL) – Rapid Research Letters
- Vol. 18 (11)
Annealing Process on Metal–Oxide–Semiconductor Channel Properties for Quasivertical GaN‐on‐Sapphire Trench Metal–Oxide–Semiconductor Field‐Effect Transistor
Quasivertical gallium nitride trench‐gate metal–oxide–semiconductor field‐effect transistors with different etch radio frequency power and the impact of the order of annealing process in tetramethylammonium hydroxide wet treatment have been fabricated and studied. The high‐power device has a threshold voltage of 5.3 V and a maximum saturation current density of 552 A cm−2, whereas the low‐power device has a threshold voltage of 4.5 V and a maximum saturation current density of 650 A cm−2. However, the low‐power device has more severe off‐state leakage due to more fixed charges and defects on the device surface. Furthermore, the annealing process serves as an additional step before wet treatment. Scanning electron mircoscope image indicates that annealing at high temperatures prior to etching can eliminate surface oxide and redistribute surface imperfections, resulting in a smoother sidewall morphology. The relationship between temperature and mobility confirms the impact of the crystal surface feature on device performance.
- 16 May 2023
- Published by American Chemical Society (ACS) in ACS Applied Materials & Interfaces
- Vol. 15 (21) , 26159-26165
Comparative Analysis of the GaN Nonpolar Plane Morphology by Wet Treatment and Its Effect on Electrical Properties in Trench MOSFET
The morphological characteristics of the GaN nonpolarsidewallswith different crystal plane orientations were studied under variousTMAH wet treatment conditions, and the effect of different morphologicalfeatures on device carrier mobility was modeled and analyzed. AfterTMAH wet treatment, the morphology of the a-planesidewall presents multiplied zigzag triangular prisms along the [0001]direction, which consist of two adjacent m-planeand c-plane on top. While along the [112 ̅0]direction, the m-plane sidewall is represented bythin, striped prisms with three m-plane and a c-plane on the side. The density and size of sidewall prismswere studied by varying the solution temperature and immersion period.The prism density decreases linearly as the solution temperature rises.With increased immersion time, both a-plane and m-plane sidewalls show smaller prism sizes. Vertical GaNtrench MOSFET with nonpolar a- and m-plane sidewall channels were fabricated and characterized. By properlytreated in TMAH solution, transistors with an a-planesidewall conduction channel exhibit higher current density, from 241to 423 A cm(-2)@V (DS) =10 V, V (GS) = 20 V, and higher mobility,from 2.9 to 2.0 cm(2) (V s)(-1), comparedto those of m-plane sidewall devices. The temperaturedependence on mobility is also discussed, and a modeling analysisfor the difference in carrier mobility is then performed.
- 16 May 2023
- Published by American Chemical Society (ACS) in ACS Applied Materials & Interfaces
- Vol. 15 (21) , 26159-26165
Comparative Analysis of the GaN Nonpolar Plane Morphology by Wet Treatment and Its Effect on Electrical Properties in Trench MOSFET
The morphological characteristics of the GaN nonpolarsidewallswith different crystal plane orientations were studied under variousTMAH wet treatment conditions, and the effect of different morphologicalfeatures on device carrier mobility was modeled and analyzed. AfterTMAH wet treatment, the morphology of the a-planesidewall presents multiplied zigzag triangular prisms along the [0001]direction, which consist of two adjacent m-planeand c-plane on top. While along the [112 ̅0]direction, the m-plane sidewall is represented bythin, striped prisms with three m-plane and a c-plane on the side. The density and size of sidewall prismswere studied by varying the solution temperature and immersion period.The prism density decreases linearly as the solution temperature rises.With increased immersion time, both a-plane and m-plane sidewalls show smaller prism sizes. Vertical GaNtrench MOSFET with nonpolar a- and m-plane sidewall channels were fabricated and characterized. By properlytreated in TMAH solution, transistors with an a-planesidewall conduction channel exhibit higher current density, from 241to 423 A cm(-2)@V (DS) =10 V, V (GS) = 20 V, and higher mobility,from 2.9 to 2.0 cm(2) (V s)(-1), comparedto those of m-plane sidewall devices. The temperaturedependence on mobility is also discussed, and a modeling analysisfor the difference in carrier mobility is then performed.