Ning Li

Conventional long-horizon finite-control-set model predictive control (FCS-MPC) for power electronics has two main real-time implementation problems: 1) calculation burden and latency; and 2) high hardware resource requirements on real-time platforms such as FPGA. To solve these problems, machine learning models have been proposed using model predictive control results as offline training data to train an artificial neural network (ANN), which will be implemented in the real-time controller instead of the original model predictive control model. In this way, the ANN reduces the online calculation burden and the hardware resource requirements. In this article, an FPGA-based 1-D convolution neural network (CNN) for long-horizon FCS-MPC is proposed. To simplify the network model and reduce the hardware resources further, model compression techniques of pruning, fine-tuning, and quantization are implemented. The proposed model is verified using a parallel hybrid converter as a case study converter, with performance and hardware resource requirements compared to conventional FCS-MPC and multilayer perceptron (MLP) models. The results show that the proposed compressed CNN model can reduce FPGA DSP resource requirements by 75% compared to a FCS-MPC model and an MLP models, while also achieving comparable or superior performance.

Fast fault current injection (FFCI) is a critical requirement for fault ride‐through compliance in voltage source converters (VSCs). A common approach to improving fault current response speed involves increasing the phase‐locked loop bandwidth, however, this can significantly compromise system stability. Thus, achieving enhanced FFCI performance without stability degradation remains a major challenge. This paper proposes a FFCI‐virtual converter system (FFCI‐VCS) control scheme, based on a virtual converter integrated with a virtual impedance network. The proposed method improves the rise time and magnitude of the fault current, enabling fast fault current injection within the first cycle (20 ms) of a grid fault, while maintaining flexible steady‐state tracking of the current reference and minimizing the impact on system stability. The system's sequence impedance is analytically modelled and validated using Simulink simulations, demonstrating that stability remains unaffected under specific parameter settings. Simulation results showing the impact of the FFC‐VCS on distance protection is presented to demonstrate how it can improve protection performance efficacy. Furthermore, hardware experiments verify the real‐time performance of the proposed FFCI‐VCS.

This article investigates the design and control of the parallel-hybrid converter (PHC), which consists of parallel connection of a silicon insulated gate bipolar transistor (IGBT) bridge and a partially rated silicon carbide (SiC) mosfet s bridge with a shared dc bus. The IGBT bridge processes the bulk of the power, while switching at a low frequency to maximize efficiency, while the SiC mosfet s bridge's lower relative switching loss is exploited to filter low-order harmonics from the IGBT bridge. A finite-set model predictive controller is detailed that allows IGBT switching frequencies down to 1 kHz to be achieved while also tightly controlling the magnitude of current in the SiC bridge. A genetic algorithm is utilized to automatically tune the control and investigate the design of the output filter as well as the influence of the controller time-step and horizon length on the performance. Power loss estimates of a 1.5 MW application case are made showing potential for significant power-loss reductions. Experimental tests validate an field-programmable gate array (FPGA) implementation of the controller and topologies performance, with IGBT bridge frequencies below 1.2 kHz and grid-current total harmonic distortion below 3% achieved. The ability of converter to switch operation between a high-current and a low-current mode and dynamic performance is also verified.