Kaan Balaban

This letter presents the design and experimental characterization of a power amplifier (PA) (245–295 GHz) with power added efficiency (PAE) of 4.54% and saturated output power of 16.7 dBm using 0.13- $\mu $ m silicon-germanium (SiGe) technology. The realized two-stage PA differential cascode cells are combined by a four-way transmission lines (T-lines)-based combiner with 1.16 dB of loss. The size of the overall chip is 1.09mm² including the pads and baluns. The presented PA achieves 2 dB higher saturated output power and 1.39% higher PAE than the state-of-the-art silicon-based PAs.

We present an integrated frequency multiplier-by-six (sextupler) for signal generation at $J$ -band (220–325 GHz) frequencies. Typically, multiplication-by-six in state-of-the-art designs is achieved by cascading frequency tripler and doubler circuits. In contrast, we propose to accomplish the multiplication-by-six in a single bootstrapped Gilbert cell (BGC) by leveraging odd-harmonic generation in the transconductance stage and self-mixing in the switching quad. A circuit analysis of the harmonic generation and mixing mechanisms is presented and verified through simulations. The sextupler is combined with a balance-compensated transformer (TF) balun at the input and a cascode amplification stage to increase the output power. As proof-of-concept, a prototype is fabricated in an advanced 130-nm SiGe BiCMOS technology with a core area of only 0.06 mm ² . The circuit demonstrates a measured peak conversion gain (CG) of 7 dB and output power of up to 4.3 dBm at 257 GHz with a dc power consumption of 119 mW, resulting in a leading-edge dc-to-RF efficiency of 2.2%. All undesired harmonics are suppressed by more than 20 dBc over the entire 3-dB bandwidth, ranging from 238–278 GHz. Compared to recently published silicon-based frequency sextuplers operating at similar frequencies, our proposed single-stage approach results in a significant reduction of dc power and silicon area, while maintaining a superior dc-to-RF efficiency and competitive output power.

This letter presents the design and experimental characterization of a highly efficient WR3.4-band power amplifier (PA) using 0.13- $\mu$ m SiGe technology. The realized differential cascode PA demonstrates a high efficiency, owing to the gm-boosting technique which enables a relatively higher small-signal gain per stage. The proposed PA exhibits a saturated output power of 10.48 dBm with a maximum power-added-efficiency (PAE) of 5.46% at 240 GHz , which is a leading-edge performance among the reported silicon (Si)-based WR3.4-band PAs. The small-signal gain peaks at 24.1 dB and the PA has a 3-dB bandwidth of 21 GHz.