Yongwen Wang

Loops constitute a small fraction of static code but dominate dynamic execution time and control overhead, posing significant challenges for energy-efficient mobile and embedded processors. This paper introduces Loop Semantic Recognition (LSR) , a microarchitectural technique that dynamically infers loop semantics to eliminate loop control overhead without requiring compiler support or ISA extensions. We further propose three complementary optimizations: Branch Strength Reduction (BSR), Hardware Loop Unrolling (HLU), and Stride Value Prediction (SVP), which progressively remove redundant control instructions, reduce pipeline pressure, and optimize loop execution. Evaluation on TSVC, PolyBench, NPB, and Swan benchmarks demonstrates that LSR and its extensions deliver substantial efficiency and energy benefits. HLU reduces committed instructions by up to 33.23% , while SVP lowers executed instructions by as much as 46.59% . LSR also reduces loop branch mispredictions and consistently decreases dynamic energy consumption, achieving an average processor-wide Energy-Delay Product (EDP) improvement of 8.36% across these four benchmark suites on a 2-wide baseline core. Scaling to a 4-wide core further raises the average EDP reduction to 15.39% . Additionally, LSR maintains consistent effectiveness across compiler optimization levels from -O1 to -O3 , confirming its robustness to code generation strategies. A complementary evaluation of SPEC CPU2017 shows an average EDP reduction of 2.93% , indicating that LSR optimization opportunities also exist in general-purpose workloads. These results are achieved with only 0.45 KB of total storage overhead, confirming LSR as a lightweight and practical solution for improving energy efficiency across mobile and embedded processor designs.

Triple Sparse General Matrix-Matrix Multiplication (TriSpGEMM) is a major performance bottleneck in scientific computing and graph analytics. Existing domain-specific accelerators support only Sparse General Matrix-Matrix Multiplication (SpGEMM). Performing TriSpGEMM by sequencing two SpGEMM kernels introduces a global synchronization barrier, forces intermediate data to be written to and read from off-chip memory, and leads to frequent pipeline stalls, all of which significantly degrade performance. A natural solution is to design a fused architecture that executes TriSpGEMM directly, but such a design must overcome three key challenges, i.e., pipeline overflow caused by highly irregular and bursty sparse dataflows, locality inefficiency stemming from the trade-off between input reuse and output aggregation, and severe head-of-line blocking due to variable memory access latencies. In this work, we present TRIDENT, a transient-data-centric accelerator for fused TriSpGEMM processing. TRIDENT integrates a hierarchical flow-control mechanism, a hybrid dataflow co-designed with a windowed sparse format, and an out-of-order decoupled execution scheme to ensure pipeline stability, locality efficiency, and latency tolerance. Comprehensive evaluations demonstrate that TRIDENT achieves an average of 3.56× performance speedup over state-of-the-art SpGEMM accelerators, and up to 49.6× and 6.3× improvements over CPU and GPU baselines, respectively.

LLC hardware prefetchers are a pivotal technique in modern high-performance processors for hiding memory access long latency. However, even accurate prefetch requests generated by LLC prefetchers experience long latency when they must traverse the LLC before accessing off-chip main memory. To reduce latency of the off-chip prefetch request generated by LLC prefetchers, we propose Artemis, an off-chip prefetch prediction approach. Artemis employs a neural predictor with confidence learning mechanism to predict whether a prefetch request generated by LLC prefetchers will miss in the LLC. When a miss is predicted, Artemis issues a speculative prefetch request directly to the main memory controller, while the regular prefetch request concurrently accesses the LLC. If Artemis's prediction is correct, the regular prefetch request eventually misses in the LLC and waits for the speculative request to return the data fetched from main memory. By doing so, Artemis hides the LLC access latency from the critical path of off-chip prefetch requests. Our extensive evaluation on diverse workloads demonstrates that Artemis provides consistent performance improvements across a wide range of system configurations, including varying core counts, state-of-the-art hardware prefetchers, LLC access latencies, and main memory bandwidths, while incurring only 9.38 KB of storage overhead.

Accelerating load requests is an effective way to improve processor performance through reducing load request latency. Currently, state-of-the-art methods, including Hermes and TLP, are limited to accelerating off-chip load requests that are correctly predicted and cannot accelerate mispredicted off-chip load requests and any on-chip load requests. To overcome this limitation, we propose a new technique called Apollo that integrates TLP. The key innovation of Apollo lies in its transformation of the perceptron-based off-chip prediction paradigm, pioneered by Hermes, into a comprehensive multi-level cache miss prediction technique. The workflow of Apollo is as follows: (1) predicting whether a load request will miss the L1D or L2, and (2) performing arbitration to decide whether to issue a speculative load request and to which cache level the request is issued, and (3) issuing a speculative load request to the lower-level cache (either L2 or LLC) after arbitration for those predicted to miss the L1D or L2, while allowing the regular load request to concurrently access the cache hierarchy. If the prediction is correct, the regular load request eventually misses the L1D or L2 and waits for the speculative load request to finish. Therefore, Apollo can hide the L1D access latency for correctly predicted L1D miss load requests, and both L1D and L2 access latency for correctly predicted L2 miss load requests. To enable Apollo, we propose a lightweight L1D miss load predictor (L1MP), a lightweight L2 miss load predictor (L2MP), and an arbiter called Athena. L1MP and L2MP predict whether load requests will miss in the L1D and L2, respectively, while Athena performs arbitration to control the issuance of speculative load requests. Our evaluation using a diverse set of workloads shows that Apollo provides a geometric mean (geomean) performance improvement of 15.2% for the single-core processor, outperforming Hermes by 9.6% and TLP by 6.4%. For the multi-core processor, Apollo provides a geomean performance improvement of 18.5%, which is 16.8% higher than Hermes and 5.8% higher than TLP.

The integrate-and-dump filter is a core component of satellite navigation receivers, enabling the tracking of navigation satellite signals and significantly influencing receiver performance. Currently, satellite navigation receivers, particularly onboard unmanned aerial vehicles (UAVs), are vulnerable to spoofing. Whether counterfeit signals can successfully hijack a receiver depends critically on how these signals alter the integrate-and-dump filter output. Existing research on satellite navigation spoofing often uses an output signal model for the integrate-and-dump filter derived from continuous-time integration. However, this model deviates from practical implementation because most modern navigation receivers are built on digital circuits that approximate continuous-time integration through discrete-time accumulation. Consequently, the discrete-time nature of actual hardware introduces errors that are not captured by the conventional continuous-time model. In this study, a mathematical model for the output signal of an integrate-and-dump filter was implemented via discrete-time accumulation. The accuracy of the proposed model was verified through simulations, and a comparative analysis with the traditional continuous-time integration model was conducted to highlight the impact of discretization errors.

Recent strides in hardware-accelerated ray tracing have propelled algorithms once deemed suitable only for offline rendering, like Monte Carlo path tracing, into interactive frame rates. While path tracing has been regarded as a practical utility in animating scenes for the film industry, achieving visually noise-free imagery often mandates thousands of samples per pixel and considerable computation time. Regrettably, this poses a difficulty for video games and virtual reality applications, which demand high frame rates and resolutions, thereby constraining the computational overhead of path tracing. Two extant approaches, in-process sampling, and post-processing reconstruction methods, i.e., denoising and upsampling, address this challenge. The giant evolution of deep learning technology has emerged as pivotal in path tracing processing. We explore and advance Monte Carlo path tracing technology based on deep learning. Moreover, we illustrate the merits and demerits of diverse designs and technologies, propose potential future development trends, and aim at providing researchers with a comprehensive understanding of the cutting-edge in deep learning-driven Monte Carlo path tracing.