Sujit Kumar

The thermal characteristics of large area GaN HEMTs on 200 mm QST engineered substrates are compared to those on GaN-on-Si. The thermal conductivity (TC) of the superlattice (SL) epitaxial buffer layers and the buried oxide layer (BOX) on the QST substrates are extracted through Raman thermography combined with 3-D finite element method (FEM) thermal simulations. The thermal resistance of large area transistors on QST is up ~1/3 lower than equivalent transistors on GaN-on-Si substrates. Transient device thermal simulation also demonstrates that QST substrates are advantageous for thermal management during switching operations, despite the buried oxide layer.

AlGaN/GaN based high-electron-mobility transistors utilize the excellent electronic and transport properties of Gallium Nitride and related compounds, making them highly sought after for high-power and high-frequency applications. However, threading dislocations that form during the GaN epitaxy growth on lattice mismatched Si substrates impact the device performance and reliability by causing an early breakdown and carrier trapping phenomena. For applications exceeding 1 kV, the growth of thick GaN stacks on 200 mm Si wafers introduces significant strain, compromising substrate integrity. This has triggered the development of engineered substrates for GaN epitaxy and the re-evaluation of the subsequent epitaxial growth. In this study, we have investigated the current transport properties of detrimental dislocations in AlGaN/GaN heterostructures grown on AlN engineered substrates (commonly referred to as QST ^® ) and on conventional Si (111) substrates. This study has been achieved by developing a correlative nanoscale characterization methodology implementing conductive atomic force microscopy, cathodoluminescence microscopy, and electron channelling contrast imaging and revisiting dislocation-sensitive etching behavior. This allowed us to observe vertical conduction paths manifesting themselves only in certain types of dislocations and to analyse the associated current transport mechanisms. Our modelling of the local current-voltage characterization on such dislocations, which are only 1% of the total dislocation density, directly associate them to the conduction mechanism via Poole-Frenkel emission in the reverse bias and variable range hopping in the reverse bias.

In this article, we present dual-gate bidirectional switches (BDSs) rated for 1200-V operation in both positive and negative biases, fabricated on 200-mm GaN-on-QST¹ engineered substrates. The switches are p-GaN gate enhancement-mode (E-mode) high-electron-mobility transistors (HEMTs) that can conduct the current and block the voltage in both directions (drain to source or source to drain). The switches are fabricated with different design variations in the channel length and field-plates (FPs) configuration and are tested in all four conduction modes (on-state, forward and reverse diode modes, and off-state). In addition, a hard breakdown of the device well above the rated voltage is demonstrated, along with initial reliability tests that demonstrate promising performance of the devices.

Time-dependent conduction in epitaxial superlattice (SL) strain relief layers of GaN high electron mobility transistors on 200 mm engineered substrates with a poly-AlN core was observed and analyzed. This phenomenon occurs when the devices were operated with substrate bias of ∼−300 V for 101–103 s. The formation of the conduction path is related to trap-assisted leakage through the SLs on the engineered substrates; de-trapped carriers spread out vertically and laterally within a portion of the SLs, leading to a higher electrical field across the rest of the layers. This conduction mechanism may be hidden during the devices' normal operation (target 650–1200 V). It could lead to undesired effects during the operation of the devices, such as a time-dependent dynamic Ron. More resistive SLs will potentially reduce the impact of this phenomenon.

This letter experimentally demonstrates 1.2 kV normally-off p-GaN gate lateral high-electron-mobility transistors (HEMTs) on 200 mm diameter engineered substrates. The fabricated p-GaN gate HEMT with optimum gate-drain spacing exhibits a threshold voltage (V _th ) of 3.2 V, an ON/OFF ratio of 10 ⁸ , low specific ON-resistance (R _on,sp ) of 5.8 mΩ-cm ² and hard breakdown voltage (V _bd ) at 1800 V. Optimized devices also show good wafer scale uniformity (σ R_on = 1.2%) for the evaluated electrical parameters and passed on-wafer high temperature gate bias (HTGB) and reverse bias stress tests without device failures.