Grayson M. Noah

Efficient thermal management is critical for cryogenic CMOS circuits, where local heating can compromise device performance and qubit coherence. Understanding heat flow at the nanoscale in these multilayer architectures requires localized, high-resolution thermal probing techniques capable of accessing buried structures. Here, we introduce a sideband thermal wave detection scheme for Scanning Thermal Microscopy, S-STWM, to probe deeply buried heater structures within CMOS dies. By extracting the phase of propagating thermal waves, this method provides spatially resolved insight into heat dissipation pathways through complex multilayer structures. Our approach enables quantitative evaluation of thermal management strategies, informs the design of cryo-CMOS circuits, and establishes a foundation for in situ thermal characterization under cryogenic operating conditions.

On-chip thermometry at deep-cryogenic temperatures is vital in quantum computing applications to accurately quantify the effect of increased temperature on qubit performance. In this work, we present a sub-1 K temperature sensor in CMOS technology based on the temperature dependence of the critical current of a superconducting (SC) thin-film. The sensor is implemented in 22-nm fully depleted silicon on insulator technology and comprises a 6-nA-resolution current-output digital-to-analog converter (DAC), a transimpedance amplifier with a SC thin-film as a gain element, and a voltage comparator. The circuit dissipates 1.5 μW and is demonstrated operating at ambient temperatures as low as 15 mK, providing a variable temperature resolution reaching sub-10 mK.

As quantum processors grow in complexity, new challenges arise such as the management of device variability and the interface with supporting electronics. Spin qubits in silicon quantum dots can potentially address these challenges given their control fidelities and potential for compatibility with large-scale integration. Here we report the integration of 1,024 independent silicon quantum dot devices with on-chip digital and analogue electronics, all operating below 1 K. A high-frequency analogue multiplexer provides fast access to all devices with minimal electrical connections, allowing characteristic data across the quantum dot array to be acquired and analysed in under 10 min. This is achieved by leveraging radio-frequency reflectometry with state-of-the-art signal integrity, characterized by a typical signal-to-noise voltage ratio in excess of 75 for an integration time of 3.18 μs. We extract key quantum dot parameters by automated machine learning routines to assess quantum dot yield and understand the impact of device design. We find correlations between quantum dot parameters and room-temperature transistor behaviour that could be used as a proxy for in-line process monitoring.

Semiconductor integrated circuits operated at cryogenic temperature will play an essential role in quantum computing architectures. These can offer equivalent or superior performance to their room-temperature counterparts while enabling a scaling up of the total number of qubits under control. Silicon integrated circuits can be operated at a temperature stage of a cryogenic system where cooling power is sufficient (~3.5+ K) to allow for analog signal chain components (e.g., amplifiers and mixers), local signal synthesis, signal digitization, and control logic. A critical stage in cryo-electronics development is the characterization of individual transistor devices in a particular technology node at cryogenic temperatures. This data enables the creation of a process design kit (PDK) to model devices and simulate integrated circuits operating well below the minimum standard temperature ranges covered by foundry-released models (e.g., -55 °C). Here, an efficient approach to the characterization of large numbers of components at cryogenic temperature is reported. We developed a system to perform dc measurements with Kelvin sense of individual transistors at 4.2 K using integrated on-die multiplexers, enabling bulk characterization of thousands of devices with no physical change to the measurement setup.

Accurate on-chip temperature sensing is critical for the optimal performance of modern complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs), to understand and monitor localized heating around the chip during operation. The development of quantum computers has stimulated much interest in ICs operating at deep cryogenic temperatures (typically 0.01–4 K), in which the reduced thermal conductivity of silicon and silicon oxide and the limited cooling power budgets make local on-chip temperature sensing even more important. Here, we report four different methods for on-chip temperature measurements native to CMOS industrial fabrication processes. These include secondary and primary thermometry methods and cover conventional thermometry structures used at room temperature as well as methods exploiting phenomena that emerge at cryogenic temperatures, such as superconductivity and Coulomb blockade. We benchmark the sensitivity of the methods as a function of temperature and use them to measure local excess temperature produced by on-chip heating elements. Our results demonstrate thermometry methods that may be readily integrated in CMOS chips with operation from the millikelvin range to room temperature.