Ziyuan Wen

Wireless minimally invasive bioelectronic implants enable a wide range of applications in healthcare, medicine, and scientific research. Magnetoelectric (ME) wireless power transfer (WPT) has emerged as a promising approach for powering miniature bio-implants because of its remarkable efficiency, safety limit, and misalignment tolerance. However, achieving low-power and high-quality uplink communication using ME remains a challenge. This paper presents a pulse-width modulated (PWM) ME backscatter uplink communication enabled by a switched-capacitor energy extraction (SCEE) technique. The SCEE rapidly extracts and dissipates the kinetic energy within the ME transducer during its ringdown period, enabling time-domain PWM in ME backscatter. Various circuit techniques are presented to realize SCEE with low power consumption. This paper also describes the high-order modeling of ME transducers to facilitate the design and analysis, which shows good matching with measurement. Our prototyping system includes a millimeter-scale ME implant with a fully integrated system-on-chip (SoC) and a portable transceiver for power transfer and bidirectional communication. SCEE is proven to induce >50% amplitude reduction within 2 ME cycles, leading to a PWM ME backscatter uplink with 17.73 kbps data rate and 0.9 pJ/bit efficiency. It also achieves 8.5 × 10 ^-5 bit-error-rate (BER) at a 5 cm distance, using a lightweight multi-layer-perception (MLP) decoding algorithm. Finally, the system demonstrates continuous wireless neural local-field potential (LFP) recording in an in vitro setup.

Analog compute-in-memory (CIM) in static random access memory (SRAM) is promising for accelerating deep learning inference by circumventing the memory wall and exploiting ultra-efficient analog low-precision arithmetic. Latest analog CIM designs attempt bit-parallel (BP) schemes for multi-bit analog matrix-vector multiplication (MVM), aiming at higher energy efficiency, throughput, and training simplicity and robustness over conventional bit-serial (BS) methods that digitally shift-and-add multiple partial analog computing results. However, BP operations require more complex analog computations and become more sensitive to well-known analog CIM challenges, including large cell areas, inefficient and inaccurate multi-bit analog operations, and vulnerability to PVT variations. This article presents PICO-RAM, a PVT-insensitive and compact CIM SRAM macro with charge-domain BP computation. It adopts a multi-bit thin-cell multiply-accumulate (MAC) unit that shares the same transistor layout as the most compact 6T SRAM cell. All analog computing modules, including digital-to-analog converters (DACs), MAC units, analog shift-and-add, and analog-to-digital converters (ADCs), reuse one set of local capacitors inside the array, performing in situ computation to save area and enhance accuracy. A compact 8.5-bit dual-threshold time-domain ADC power gates the main path most of the time, leading to a significant energy reduction. Our 65-nm prototype achieves the highest weight storage density of 559 Kb/mm $^2$ and exceptional robustness to temperature and voltage variations ( $-$ 40 $^\circ$ C to 105 $^{\circ}$ C and 0.65 to 1.2 V) among SRAM-based analog CIM designs.

Regular pattern matching is pervasive in applications such as text processing, malware detection, network security, and bioinformatics. Recent studies have demonstrated specialized in-memory automata processors with superior energy and memory efficiencies than existing computing platforms. Yet, they lack efficient support for the construct of bounded repetition that is widely used in regular expressions (regexes). This paper presents BVAP, a software-hardware co-designed in-memory Bit Vector Automata Processor. It is enabled by a novel theoretical model called Action-Homogeneous Non-deterministic Bit Vector Automata (AH-NBVA), its efficient hardware implementation, and a compiler that translates regexes into hardware configurations. BVAP is evaluated with a cycle-accurate simulator in a 28nm CMOS process, achieving 67-95% higher energy efficiency and 42-68% lower area, compared to state-of-the-art automata processors (CA, eAP, and CAMA), across a set of real-world benchmarks.