Yeon Ho Kim

Two-dimensional (2D) semiconductors, with their atomically thin geometry and excellent electrostatic control, are promising channel materials for ferroelectric field-effect transistors (FeFETs). However, integrating high-quality ferroelectric gate stacks onto these ultrathin channels in a manner compatible with modern semiconductor manufacturing, particularly under back-end-of-line (BEOL) constraints, remains a major challenge primarily due to interfacial instability. Here, we demonstrate interface-engineered top-gated 2D FeFETs based on monolayer molybdenum disulfide (MoS2) integrated with ferroelectric hafnium–zirconium oxide (HZO) via atomic layer deposition. An ultrathin high-κ yttrium oxide (Y2O3) interfacial layer serves as both a nucleation and protection layer, enabling conformal HZO growth while preserving a sharp van der Waals interface. All fabrication steps were conducted below 300 °C, fully satisfying BEOL thermal budgets. The resulting devices exhibit intrinsic polarization-driven switching rather than trap-dominant behavior. Notably, they achieve a nearly ideal memory window of 3.6 V, corresponding to ∼90% of the theoretical maximum, under a low operating voltage of ±3.5 V, along with distinguishable nonvolatile switching characteristics. These results establish a CMOS and BEOL-compatible interface engineering strategy for integrating high-performance 2D FeFETs, providing a scalable pathway toward monolithic 3D systems for future embedded memory and logic-in-memory applications.

A gate stack that facilitates a high‐quality interface and tight electrostatic control is crucial for realizing high‐performance and low‐power field‐effect transistors (FETs). However, when constructing conventional metal‐oxide‐semiconductor structures with two‐dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high‐quality gate dielectrics through native oxidation or film deposition. Here, a gate‐dielectric‐less device architecture of van der Waals Schottky gated metal–semiconductor FETs (vdW‐SG MESFETs) using a molybdenum disulfide (MoS₂) channel and surface‐oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, −1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi‐level (E_F) pinning‐free gate stack at the Schottky–Mott limit. Furthermore, authors experimentally and theoretically confirm that E_F depinning can be achieved by suppressing both metal‐induced and disorder‐induced gap states at the interface between the monolithic‐oxide‐gapped metal gate and the MoS₂ channel. This work paves a new route for designing high‐performance and energy‐efficient 2D electronics.