Interface-Engineered Hafnia–MoS2 Ferroelectric Field-Effect Transistors Enabling a Nearly Ideal Memory Window with Back-End-of-Line Compatibility
Open Access
- 30 August 2026
- journal article
- Published by American Chemical Society (ACS) in ACS Nano
- Vol. 20 (36) , 24857-24866
Abstract
Two-dimensional (2D) semiconductors, with their atomically thin geometry and excellent electrostatic control, are promising channel materials for ferroelectric field-effect transistors (FeFETs). However, integrating high-quality ferroelectric gate stacks onto these ultrathin channels in a manner compatible with modern semiconductor manufacturing, particularly under back-end-of-line (BEOL) constraints, remains a major challenge primarily due to interfacial instability. Here, we demonstrate interface-engineered top-gated 2D FeFETs based on monolayer molybdenum disulfide (MoS2) integrated with ferroelectric hafnium–zirconium oxide (HZO) via atomic layer deposition. An ultrathin high-κ yttrium oxide (Y2O3) interfacial layer serves as both a nucleation and protection layer, enabling conformal HZO growth while preserving a sharp van der Waals interface. All fabrication steps were conducted below 300 °C, fully satisfying BEOL thermal budgets. The resulting devices exhibit intrinsic polarization-driven switching rather than trap-dominant behavior. Notably, they achieve a nearly ideal memory window of 3.6 V, corresponding to ∼90% of the theoretical maximum, under a low operating voltage of ±3.5 V, along with distinguishable nonvolatile switching characteristics. These results establish a CMOS and BEOL-compatible interface engineering strategy for integrating high-performance 2D FeFETs, providing a scalable pathway toward monolithic 3D systems for future embedded memory and logic-in-memory applications.Keywords
Funding Information
- Electric Power Research Institute of Seoul National University
- BK21 FOUR program of the Education and Research Program for Future ICT Pioneers
- National Research Foundation of Korea (RS-2023-00258309)
- National Research Foundation of Korea (RS-2023-NR077272)
- Seoul National University
- Samsung Electronics (IO230413-05924-01)
- Samsung Electronics (SRFC-MA2402-02)
This publication has 50 references indexed in Scilit:
- Sub-Nanometer Equivalent Oxide Thickness and Threshold Voltage Control Enabled by Silicon Seed Layer on Monolayer MoS2 TransistorsNano Letters, 2025
- Reconfigurable Multifunctional van der Waals Ferroelectric Devices and Logic CircuitsACS Nano, 2023
- Recent Advances and Future Prospects for Memristive Materials, Devices, and SystemsACS Nano, 2023
- Enhancing Memory Window Efficiency of Ferroelectric Transistor for Neuromorphic Computing via Two‐Dimensional Materials IntegrationAdvanced Functional Materials, 2023
- Sub-Nanosecond Switching of Si:HfO2 Ferroelectric Field-Effect TransistorNano Letters, 2023
- Post-CMOS Compatible Aluminum Scandium Nitride/2D Channel Ferroelectric Field-Effect-Transistor MemoryNano Letters, 2021
- Review of ferroelectric field‐effect transistors for three‐dimensional storage applicationsNano Select, 2021
- Ferroelectrically Gated Atomically Thin Transition‐Metal Dichalcogenides as Nonvolatile MemoryAdvanced Materials, 2016
- Interface Engineering for High‐Performance Top‐Gated MoS2 Field‐Effect TransistorsAdvanced Materials, 2014
- MoS2 Nanosheets for Top‐Gate Nonvolatile Memory Transistor ChannelSmall, 2012