Princy Sharma
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Princy Sharma has a total of 2 co-authors. Here are the top co-authors by number of shared publications:
Subindu Kumar
Department of Electronics Engineering, IIT (ISM) Dhanbad, India
2 shared publications- Pankaj Kumar
Department of Electronics and Communication Engineering, Indian Institute of Information Technology Dharwad, Karnataka, India
1 shared publication
Latest Publications
- 1 November 2025
- Published by IOP Publishing in Physica Scripta
- Vol. 100 (11) , 115920
Source/drain series resistance and fabrication-induced variabilities in the characteristics of gate-all-around junctionless silicon nanowire FET and associated CMOS circuit
The gate-all-around junctionless transistor (GAA-JLT) is anticipated to dominate future technology nodes considering the immunity of the device to the adverse effects of constant downscaling. In this work, we have developed an analytical model for a short channel GAA-JLT taking into account the impact of source/drain series resistance ( R sd ) on various electrical parameters of the device. The inclusion of R sd in the model result in transcendental nature of expressions. Multi-iterative algorithms have been presented to evaluate the analytical model. We have shown that the negligence of R sd in short channel device modeling may contribute to a significant overestimation of drain current. Furthermore, the cross-sectional variability in the channel region induced due to the shortcomings inherent to the fabrication process is modeled by elliptical structure characterized by its aspect ratio ( AR ). The variation in channel AR modifies the effective radius of the GAA-JLT, which has been incorporated in the analytical model for accurate computations. The proposed model is employed to study the static and transient characteristics of a CMOS inverter realized based on the device through the use of iterative algorithms Finally, we have examined the effect of multiple-channels and channel AR variability on the characteristics of the CMOS inverter. Our computations reveal that, incorporating series resistance along with cross-section variability result in an efficient analytical model for the GAA-JLT and associated digital circuits.
- 1 November 2025
- Published by IOP Publishing in Physica Scripta
- Vol. 100 (11) , 115920
Source/drain series resistance and fabrication-induced variabilities in the characteristics of gate-all-around junctionless silicon nanowire FET and associated CMOS circuit
The gate-all-around junctionless transistor (GAA-JLT) is anticipated to dominate future technology nodes considering the immunity of the device to the adverse effects of constant downscaling. In this work, we have developed an analytical model for a short channel GAA-JLT taking into account the impact of source/drain series resistance ( R sd ) on various electrical parameters of the device. The inclusion of R sd in the model result in transcendental nature of expressions. Multi-iterative algorithms have been presented to evaluate the analytical model. We have shown that the negligence of R sd in short channel device modeling may contribute to a significant overestimation of drain current. Furthermore, the cross-sectional variability in the channel region induced due to the shortcomings inherent to the fabrication process is modeled by elliptical structure characterized by its aspect ratio ( AR ). The variation in channel AR modifies the effective radius of the GAA-JLT, which has been incorporated in the analytical model for accurate computations. The proposed model is employed to study the static and transient characteristics of a CMOS inverter realized based on the device through the use of iterative algorithms Finally, we have examined the effect of multiple-channels and channel AR variability on the characteristics of the CMOS inverter. Our computations reveal that, incorporating series resistance along with cross-section variability result in an efficient analytical model for the GAA-JLT and associated digital circuits.