Silong Chen

This paper presents a high-resolution analog front-end (AFE) circuit. The AFE integrates a low-noise current amplifier and a second-order delta-sigma modulator (DSM). Implemented in 22nm Fully Depleted Silicon-On-Insulator (FD-SOI) technology, the amplifier achieves a bandwidth of 16MHz with gain up to MΩ-range at 10 kHz. The measured input current noise densities reach 38.56 fA/√Hz at 1 Hz and 21.28 fA/√Hz at 10 Hz, while maintaining a common-mode rejection ratio (CMRR) of 162 dB. The DSM operates under 1.2 V supply voltage with 12.8 MHz sampling frequency, demonstrating 91.3 dB SNDR, 13.9-bit ENOB, and 160.44 dB FoMSNDR at 3.66 mW power consumption. Benefiting from the noise suppression and interference immunity of FD-SOI technology, the proposed design demonstrates low-noise characteristics, low-power consumption, and an enhanced CMRR. It addresses engineering implementation pain points such as "high noise interference, high power consumption, and insufficient accuracy" in weak current signal detection, and provides a highly reliable hardware solution for signal acquisition needs in fields including biomedical applications, industrial sensing, and precision instruments.

This article presents a 6.78 MHz single-stage wireless power transfer receiver (RX) using 0X/1X regulating rectifier with improved voltage mode (VM) delay compensation for implantable medical devices (IMDs). The regulation of 0X/1X modes is achieved through pulse width modulation (PWM), with the frequency set at 1/16 of the carrier clock to ensure circuit stability and enhance power conversion efficiency (PCE) under light loads. VM delay compensation has the advantage of power consumption. However, the traditional VM on-delay compensation may become ineffective because a large voltage pulse will occur on the RX side input when the circuit delays increase. Therefore, an improved VM on-delay compensation method is proposed. Coarse compensation for on-delays can be achieved by reusing the control signal generated from off-delay compensation loop, as off-delay compensation processes will not be influenced by on-delay compensation processes. It allows the on-delay compensation loop to function normally and finely compensate for on-delays. The proposed rectifier is designed in 0.18μm CMOS process. It can achieve output voltage management of 1.8V. Comparing with other regulating rectifier, the proposed rectifier has a fast transient response of 14 μs and a small chip area of 0.91 mm ² . The simulation results indicate that this rectifier can attain high PCE of 84.6% in light load (500Ω) and peak PCE of 93.5% in heavy load (50Ω). The high voltage conversion ratio (VCR) of over 93% is also achieved under the large circuit delays.