Alexandre Kennedy Pinto Souza

This work presents a novel compact CMOS potentiostat-designed circuit for an electrochemical cell. The proposed topology functions as a circuit interface, controlling the polarization of voltage signals at the sensor electrodes and facilitating current measurement during the oxidation–reduction process of an analyzed solution. The potentiostat, designed for CMOS technology, comprises a two-stage amplifier, two current mirror blocks coupled to this amplifier, and a CMOS push–pull output stage. The electrochemical method of cyclic voltammetry is employed, operating within a voltage range of ±0.8 V and scan rates of 10 mV/s, 25 mV/s, 100 mV/s, and 250 mV/s. The circuit is capable of reading currents ranging from 10 µA to 500 µA. Experimental results were obtained using a potassium ferrocyanide K₃[Fe(CN)₆] redox solution with concentrations of 10, 15, and 20 mmol/L, and their corresponding voltammograms were evaluated. The experimental results from a discrete circuit demonstrate that the proposed potentiostat topology produces outcomes consistent with those of classical topologies presented in the literature and industrial equipment.

This work presents a novel compact CMOS potentiostat designed circuit for electrochemical cell. The proposed topology functions as a circuit interface, controlling the polarization of voltage signals at the sensor electrodes and facilitating current measurement during the oxidation-reduction process of a analyzed solution. The potentiostat, designed for CMOS technology, comprises a two-stage amplifier, two current mirror blocks coupled to this amplifier, and a CMOS push-pull output stage. It employs the electrochemical method of cyclic voltammetry, operating within voltage range of ±0.8 V and scan rates of 10mV/s, 25mV/s, 100mV/s and 250 mV/s. The circuit is capable of reading currents ranging from 10 µA to 500 µA. Experimental results were obtained using a potassium ferrocyanide (K3(FeCN)6) redox solution with concentrations of 10, 15 and 20 mmol/L, and their corresponding voltammograms were evaluated. The experimental results from a discrete circuit demonstrate that the proposed potentiostat topology produces outcomes consistent with those of classical topologies presented in the literature and industrial equipment.

In this work, a new compact CMOS potentiostat circuit for electrochemical sensors is proposed. Integrated Potentiostats in CMOS technology are usually found in the literature designed with operational amplifiers performing both the electrochemical sensor bias and signal readout. In order to present alternative circuitry, a new potentiostat topology composed of a two-stage operational amplifier and a current conveyor circuit is proposed. The current conveyor is employed to perform the bias signal readout of an electrochemical cell with three electrodes. Simulations and experimental results of a discrete circuit version show that the proposed potentiostat topology yields results compliant with those of classical topologies presented in the literature.

The three FET CMOS active pixel sensors (APS) operating in the linear-logarithmic mode is one of the most efficient wide-dynamic-range imagers. However, the quality of the image generated at the focal-plane array is often compromised by fixed-pattern noise (FPN) between pixels. The classical correlated double sampling (CDS) technique is used to reduce FPN in imagers operating in the linear mode. But in the complementary linear-logarithmic mode CDS does not work properly and alternative techniques must be applied to reduce FPN. The ordinary alternative techniques increase either the complexity of the pixel or its external circuitry. In order to avoid these problems a new technique was devised to reduce FPN that can be applied to the basic three FET APS architecture. With the purpose to assert the efficacy of the proposed technique a small array was fabricated in a standard 0.35 μm CMOS technology. Experimental results show that the proposed technique is able to reduce FPN quite steadily within the whole illumination range used to test the array. And therefore, the signal-to-noise-and-distortion ratio (SNDR) of the array is also improved within the whole range of operation.