Élvio Carlos Dutra e Silva Junior

In recent years, many chaos-based encryption algorithms have been proposed. Many of these are based on established designs and populate their S-boxes with values derived from chaotic maps, following conventional implementation strategies to enable comparison with their original non-chaotic counterparts. In contrast, this work proposes a novel approach: a Chaos-Based Substitution Box (CB-SBox) implementation, in which conventional ROM-based S-boxes are replaced by a digital circuit that directly executes a selected chaotic map. This method enables the construction of S-boxes with long word lengths through an FPGA-based programmable circuit that allows for variable S-box lengths, facilitating the analysis of S-boxes of varying sizes, and ultimately enhancing security, particularly for larger S-boxes, as demonstrated by increased resistance to linear and differential cryptanalysis. Furthermore, the proposed CB-SBox achieves reductions in both area and power consumption compared to size-comparable ROM-based S-boxes. A 19-bit chaos-based S-box consumes just 0.0238% of the area and 0.0241% of the power required by an equivalent ROM-implemented S-box while providing the same level of security. The inherent unpredictability of non-linear chaotic behavior causes the proposed chaos-based S-boxes to exhibit non-bijective characteristics, making them well suited for application in non-invertible cryptographic primitives, such as hash functions and Feistel networks. The proposed CB-SBox is implemented in a Feistel network as described in the literature, and the results are provided.

This work presents a novel compact CMOS potentiostat-designed circuit for an electrochemical cell. The proposed topology functions as a circuit interface, controlling the polarization of voltage signals at the sensor electrodes and facilitating current measurement during the oxidation–reduction process of an analyzed solution. The potentiostat, designed for CMOS technology, comprises a two-stage amplifier, two current mirror blocks coupled to this amplifier, and a CMOS push–pull output stage. The electrochemical method of cyclic voltammetry is employed, operating within a voltage range of ±0.8 V and scan rates of 10 mV/s, 25 mV/s, 100 mV/s, and 250 mV/s. The circuit is capable of reading currents ranging from 10 µA to 500 µA. Experimental results were obtained using a potassium ferrocyanide K₃[Fe(CN)₆] redox solution with concentrations of 10, 15, and 20 mmol/L, and their corresponding voltammograms were evaluated. The experimental results from a discrete circuit demonstrate that the proposed potentiostat topology produces outcomes consistent with those of classical topologies presented in the literature and industrial equipment.

This work presents a novel compact CMOS potentiostat designed circuit for electrochemical cell. The proposed topology functions as a circuit interface, controlling the polarization of voltage signals at the sensor electrodes and facilitating current measurement during the oxidation-reduction process of a analyzed solution. The potentiostat, designed for CMOS technology, comprises a two-stage amplifier, two current mirror blocks coupled to this amplifier, and a CMOS push-pull output stage. It employs the electrochemical method of cyclic voltammetry, operating within voltage range of ±0.8 V and scan rates of 10mV/s, 25mV/s, 100mV/s and 250 mV/s. The circuit is capable of reading currents ranging from 10 µA to 500 µA. Experimental results were obtained using a potassium ferrocyanide (K3(FeCN)6) redox solution with concentrations of 10, 15 and 20 mmol/L, and their corresponding voltammograms were evaluated. The experimental results from a discrete circuit demonstrate that the proposed potentiostat topology produces outcomes consistent with those of classical topologies presented in the literature and industrial equipment.