Yuxuan Wang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Yuxuan Wang has a total of 16 co-authors. Here are the top co-authors by number of shared publications:
- David Atienza
Embedded Systems Laboratory, EPFL, Lausanne, Switzerland
4 shared publications - Giovanni Ansaloni
EPFL, Lausanne, Vaud, Switzerland
4 shared publications - Abu Sebastian
IBM Research Europe, Rüschlikon, Switzerland
1 shared publication - Corey Lammie
IBM Research Europe, Rüschlikon, Switzerland
1 shared publication - Cristian Tirelli
USI, Switzerland
1 shared publication - Fernando Castro
Complutense University of Madrid
1 shared publication
Latest Publications
- Open Access
- 21 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
Exposing Embedded Matrix Multiplication with polyhedral transformations for CGRA compilation
Matrix-matrix multiplication ( mmul ) is a dominant computing pattern in edge workloads, but in real applications it is often embedded within larger affine programs and intertwined with other operations. Coarse-Grained Reconfigurable Arrays (CGRAs) can flexibly and efficiently support it, since they combine operation-level reconfigurability and high energy efficiency. However, mapping computational kernels that include mmul with state-of-the-art compilation strategies often leads to suboptimal results, since its multi-dimensional structure hampers the uncovering of its inherent parallelism and, ultimately, runtime performance. This paper presents Kernel-CGRA, a compiler flow that uses polyhedral transformations to expose legal affine mmul subspaces, lower each accepted region to a back-end-independent operation, and preserve the surrounding computation in the generic CDFG path. For CGRA execution, the operation is instantiated as a parametric output-stationary kernel, while residual regions are reconnected through context generation and live-value preservation. The matcher is intentionally strict: only regions proven to match the supported affine mmul form are rewritten. Across canonical, fused, and application-level benchmarks, Kernel-CGRA achieves runtime speedups of up to 10.2 × over state-of-the-art CGRA CDFG compilation with modulo scheduling and loop unrolling.
- 21 October 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
Open AccessExposing Embedded Matrix Multiplication with polyhedral transformations for CGRA compilation
Matrix-matrix multiplication ( mmul ) is a dominant computing pattern in edge workloads, but in real applications it is often embedded within larger affine programs and intertwined with other operations. Coarse-Grained Reconfigurable Arrays (CGRAs) can flexibly and efficiently support it, since they combine operation-level reconfigurability and high energy efficiency. However, mapping computational kernels that include mmul with state-of-the-art compilation strategies often leads to suboptimal results, since its multi-dimensional structure hampers the uncovering of its inherent parallelism and, ultimately, runtime performance. This paper presents Kernel-CGRA, a compiler flow that uses polyhedral transformations to expose legal affine mmul subspaces, lower each accepted region to a back-end-independent operation, and preserve the surrounding computation in the generic CDFG path. For CGRA execution, the operation is instantiated as a parametric output-stationary kernel, while residual regions are reconnected through context generation and live-value preservation. The matcher is intentionally strict: only regions proven to match the supported affine mmul form are rewritten. Across canonical, fused, and application-level benchmarks, Kernel-CGRA achieves runtime speedups of up to 10.2 × over state-of-the-art CGRA CDFG compilation with modulo scheduling and loop unrolling.
- Open Access
- 2 July 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Reconfigurable Technology and Systems
- Vol. 19 (3) , 1-27
An MLIR-Based Compilation Framework for Control Flow Management on Coarse Grained Reconfigurable Arrays
Coarse-Grained Reconfigurable Arrays (CGRAs) present both high flexibility and efficiency, making them well-suited for the acceleration of intensive workloads. Nevertheless, a key barrier towards their widespread adoption is posed by CGRA compilation, which must cope with a multi-dimensional space spanning both the spatial and the temporal domains. Indeed, state-of-the-art compilers are limited in scope, as they mostly handle data flow while providing little or no support for control flow. Hence, they mostly focus on mapping single loops and/or delegate the management of control-flow divergences to ad-hoc hardware units. Conversely, in this paper, we show that control flow can be effectively managed and optimized at the compilation level, enabling a broad set of applications to be targeted while remaining hardware-agnostic and achieving high performance. We embody our methodology in a modular compilation framework consisting of transformation and optimization passes, enabling support for applications with arbitrary control flows running on homogeneous CGRA meshes. We also introduce a novel mapping methodology that serves as a compilation back-end, addressing limitations in available CGRA hardware resources and ensuring a feasible solution during compilation. Our framework achieves up to 2.1 \(\times\) runtime speed-up over state-of-the-art approaches, purely through compilation optimizations.- 2 July 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Reconfigurable Technology and Systems
- Vol. 19 (3) , 1-27
Open AccessAn MLIR-Based Compilation Framework for Control Flow Management on Coarse Grained Reconfigurable Arrays
Coarse-Grained Reconfigurable Arrays (CGRAs) present both high flexibility and efficiency, making them well-suited for the acceleration of intensive workloads. Nevertheless, a key barrier towards their widespread adoption is posed by CGRA compilation, which must cope with a multi-dimensional space spanning both the spatial and the temporal domains. Indeed, state-of-the-art compilers are limited in scope, as they mostly handle data flow while providing little or no support for control flow. Hence, they mostly focus on mapping single loops and/or delegate the management of control-flow divergences to ad-hoc hardware units. Conversely, in this paper, we show that control flow can be effectively managed and optimized at the compilation level, enabling a broad set of applications to be targeted while remaining hardware-agnostic and achieving high performance. We embody our methodology in a modular compilation framework consisting of transformation and optimization passes, enabling support for applications with arbitrary control flows running on homogeneous CGRA meshes. We also introduce a novel mapping methodology that serves as a compilation back-end, addressing limitations in available CGRA hardware resources and ensuring a feasible solution during compilation. Our framework achieves up to 2.1 \(\times\) runtime speed-up over state-of-the-art approaches, purely through compilation optimizations. - 4 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Emerging Topics in Computing
- Vol. 13 (4) , 1383-1395
LionHeart: A Layer-Based Mapping Framework for Heterogeneous Systems With Analog In-Memory Computing Tiles
When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learning (ML) algorithms, in constant time complexity. Nonetheless, when performing computations in the analog domain, novel challenges are introduced in terms of arithmetic precision and stochasticity, due to non-ideal circuit and device behaviour. Moreover, these non-idealities have a temporal dimension, resulting in a degrading application accuracy over time. Facing these challenges, we propose a novel framework, named LionHeart, to obtain hybrid analog-digital mappings to execute Deep Learning (DL) inference workloads using heterogeneous accelerators. The accuracy-constrained mappings derived by LionHeart showcase, across different Convolutional Neural Networks (CNNs) and one transformer-based network, high accuracy and potential for speedup. The results of the full system simulations highlight runtime reductions and energy efficiency gains that exceed 6×, with a user-defined accuracy threshold for a fully digital floating point implementation.
- 4 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Emerging Topics in Computing
- Vol. 13 (4) , 1383-1395
LionHeart: A Layer-Based Mapping Framework for Heterogeneous Systems With Analog In-Memory Computing Tiles
When arranged in a crossbar configuration, resistive memory devices can be used to execute Matrix-Vector Multiplications (MVMs), the most dominant operation of many Machine Learning (ML) algorithms, in constant time complexity. Nonetheless, when performing computations in the analog domain, novel challenges are introduced in terms of arithmetic precision and stochasticity, due to non-ideal circuit and device behaviour. Moreover, these non-idealities have a temporal dimension, resulting in a degrading application accuracy over time. Facing these challenges, we propose a novel framework, named LionHeart, to obtain hybrid analog-digital mappings to execute Deep Learning (DL) inference workloads using heterogeneous accelerators. The accuracy-constrained mappings derived by LionHeart showcase, across different Convolutional Neural Networks (CNNs) and one transformer-based network, high accuracy and potential for speedup. The results of the full system simulations highlight runtime reductions and energy efficiency gains that exceed 6×, with a user-defined accuracy threshold for a fully digital floating point implementation.
- 25 September 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Biomedical Circuits and Systems
- Vol. 19 (1) , 82-92
ACE: Automated Optimization Towards Iterative Classification in Edge Health Monitors
Wearable devices for health monitoring are essential for tracking individuals’ health status and facilitating early detection of diseases. However, processing biomedical signals online for real-time monitoring is challenging due to limited computational resources on edge devices. To address this challenge, we propose an application-agnostic methodology called ACE (Automated optimization towards classification on the Edge). ACE converts a health monitoring algorithm with feature extraction and classification into an iterative detection process, incorporating algorithms of varying complexities and minimizing re-computation of shared data. First, ACE decomposes a monolithic model, employing a single feature set and classifier, into multiple algorithms with different computational complexities. Then, our automatic analysis tool integrates buffering logic into these algorithms to prevent recomsputation of shared computational-intensive data. The optimized algorithm is then converted into a low-level language in C for deployment. During runtime, the system initiates monitoring with the lowest complexity algorithm and iteratively involves algorithms with higher complexity without recomputing the existing data. The iteration process continues until a pre-defined confidence threshold is met. We demonstrate the effectiveness of ACE on two biomedical applications: seizure detection and emotional state classification. ACE achieves at least 28.9% and 18.9% runtime savings without any accuracy loss on a Cortex-A9 edge platform for the two benchmarks, respectively. We discuss and demonstrate how ACE can be used by designers of such biomedical algorithms to automatically optimize and deploy their applications on the edge.
- 25 September 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Biomedical Circuits and Systems
- Vol. 19 (1) , 82-92
ACE: Automated Optimization Towards Iterative Classification in Edge Health Monitors
Wearable devices for health monitoring are essential for tracking individuals’ health status and facilitating early detection of diseases. However, processing biomedical signals online for real-time monitoring is challenging due to limited computational resources on edge devices. To address this challenge, we propose an application-agnostic methodology called ACE (Automated optimization towards classification on the Edge). ACE converts a health monitoring algorithm with feature extraction and classification into an iterative detection process, incorporating algorithms of varying complexities and minimizing re-computation of shared data. First, ACE decomposes a monolithic model, employing a single feature set and classifier, into multiple algorithms with different computational complexities. Then, our automatic analysis tool integrates buffering logic into these algorithms to prevent recomsputation of shared computational-intensive data. The optimized algorithm is then converted into a low-level language in C for deployment. During runtime, the system initiates monitoring with the lowest complexity algorithm and iteratively involves algorithms with higher complexity without recomputing the existing data. The iteration process continues until a pre-defined confidence threshold is met. We demonstrate the effectiveness of ACE on two biomedical applications: seizure detection and emotional state classification. ACE achieves at least 28.9% and 18.9% runtime savings without any accuracy loss on a Cortex-A9 edge platform for the two benchmarks, respectively. We discuss and demonstrate how ACE can be used by designers of such biomedical algorithms to automatically optimize and deploy their applications on the edge.