Taeyoung Song

Thermal atomic layer deposition (ALD) of BaTiO3 (BTO) is of interest for next-generation microelectronic devices, including RAM and NAND memory. Herein, we investigate the influence of deposition temperature on the microstructure and electronic properties of 50 nm BTO thin films fabricated by ALD at 200, 220, 240, and 280 °C using bis-(1,2,4 triisopropylcyclopentadienyl)-Ba [Ba(iPr3Cp2)], titanium isopropoxide, and water as precursors, and highlight the significance of void formation in films based on this chemistry. Self-limiting ALD behavior is observed, such that the deposition rate and Ba:Ti ratio are independent of prolonged Ba dose times. XRD shows that films deposited at 220 and 240 °C are significantly more crystalline than films deposited at 280 °C after annealing. Scanning electron microscopy reveals a difference in film microstructure depending on deposition temperature, indicative of different “structural zones”. Cross-sectional transmission electron microscopy reveals that annealed, crystallized BTO films are susceptible to void formation, especially when lower ALD deposition temperatures are used. This void formation appears to result from a combination of the microstructure of the as-deposited film and the easily hydrated barium constituent and is identified as an important structural defect that will need to be avoided to achieve desired dielectric performance. Electrical properties, such as capacitance–voltage (CV), dielectric loss, and DC current–voltage (IV), are closely correlated with microstructure. Fifty-nanometer BTO thin films deposited at 220, 240, and 280 °C have relative permittivity values (εr) of 73, 60, and 33, respectively, at 10 kHz after annealing. Dielectric loss (tanδ) is as low as 0.001. A modest dispersion in capacitance is observed across varying sampling frequencies. Future research to further understand and mitigate void formation while retaining proper stoichiometry for this ALD chemistry is recommended to further improve dielectric performance.

In this work, we report a systematic study of the impact of high-temperature post-capping thermal annealing on the memory characteristics of Oxide-semiconductor channel ferroelectric field-effect transistors (OS-FeFETs). Using an identical engineered ferroelectric gate stack—8nm Hf_0.5Zr_0.5O₂ (HZO) / 3 nm Al₂O₃ / 8 nm HZO (8/3/8)—and a hybrid capping layer (3 nm HfO₂ + 3 nm Al₂O₃), 10% Ga-doped In₂O₃ (IGO)–channel and 4% W-doped In₂O₃ (IWO)–channel FeFETs remain functional after annealing at temperatures up to 650 °C for durations of up to 30 min and 10 min, respectively; further annealing results in irreversible loss of conduction and device failure. Detailed electrical analysis reveals that the MW enhancement originates from a preferential positive shift in the erased-state threshold voltage, while the programmed-state threshold voltage remains comparatively stable. Grazing-incidence X-ray diffraction measurements further indicate structural evolution in the IWO and IGO oxide channels with increasing annealing temperature, supporting the observed electrical trends.

NAND flash forms the core of modern solid-state storage, which is critical for data-intensive AI applications, yet charge-trap NAND suffers rapid threshold-voltage (V_th) degradation under ionizing radiation, causing reliability challenges for space and defense applications. Here we show that ferroelectric field-effect transistors (FeFETs) with laminated gate stacks offer a promising route to achieving radiation resilience in vertical NAND technology. We demonstrate that large-memory-window, vertical NAND-compatible laminated poly-silicon-channel FeFETs with an 8 nm Hf_0.5Zr_0.5O₂/3 nm Al₂O₃/8 nm Hf_0.5Zr_0.5O₂ stack retain a full memory window and robust switching up to 10 Mrad(air) of the total ionizing dose (TID). Programmed and erased states show negligible TID-induced drift after 1 Mrad(air), while only the erased state degrades by ∼2 V at 10 Mrad(air). Technology computer-aided design (TCAD) modeling attributes these asymmetric shifts to state-dependent traps. Compared to charge-trap NAND, laminated FeFETs exhibit ∼30-fold lower V_th degradation per unit dose, positioning them as superior radiation-resilient storage candidates.

We investigate the impact of a monolithic 3-D (M3D) integration process-critical $400~^{\circ } $ C postprocessing forming gas annealing (FGA) on the electrical performance, reliability, and defect evolution of oxide-channel thin-film transistors (TFTs), combining systematic experiments with density-functional-theory (DFT)-based liquid-quench molecular-dynamics (MD) simulations. Indium tungsten oxide (IWO) TFTs are employed as a model system and encapsulated with a thin 3-nm Al₂O₃/3 nm HfO₂ hybrid layer that effectively suppresses external hydrogen ingress. We reveal a nonmonotonic evolution of device behavior during FGA, governed by initial densification followed by partial crystallization. Short-duration FGA (10 min) induces channel densification and the formation of shallow, delocalized defect states, leading to pronounced positive bias temperature instability (PBTI) degradation and the emergence of a characteristic transfer-curve “kink.” With prolonged annealing (>40 min), partial crystallization of the oxide channel occurs, stabilizing hydrogen in deep, localized defect states, suppressing hydrogen mobility, and restoring device reliability. As a result, the PBTI shift is reduced to 10.4 mV after 2000 s of stress, accompanied by complete elimination of the transfer-curve kink. These findings provide a mechanistic understanding of hydrogen–defect interactions during high-temperature postprocessing FGA and demonstrate that appropriate hydrogen-blocking encapsulation enables oxide-channel TFT integration without compromising electrical performance or reliability.

Advanced logic transistors require gate dielectrics that achieve subnanometer equivalent oxide thickness (EOT), suppress leakage, and satisfy three key requirements: (i) compatibility with RMG-like high-temperature processing, (ii) sufficient V_th tunability for multi-V_th design, and (iii) high device reliability. However, meeting all of these requirements at once has been difficult with conventional high-κ systems. In this work, we demonstrate that our Hf/Zr-based gate stacks quantitatively satisfy these conditions. (i) After a 700 °C N₂ anneal, the HZH superlattice achieves EOT = 7.3 Å, lower than conventional HfO₂-only stacks (8.5 Å) while maintaining comparable leakage. (ii) Embedding a 3 Å Al₂O₃ dipole within the HfO₂/ZrO₂/HfO₂ superlattice (HZHA) breaks the conventional dipole trade-off, achieving an 8.4 Å EOT─lower than the 9.0 Å of a standard HfO₂/Al₂O₃ stack─while providing a > 200 mV V_FB shift, thereby enabling multi-V_th tuning without compromising scaling. (iii) Furthermore, under -2 V negative-bias temperature stress at 125 °C for 100 s, HZHA and HA exhibit comparable V_FB drifts of 87 mV and 97 mV, respectively, confirming that strong V_th tunability and subnanometer EOT can be achieved without compromising stability. In addition to these quantitative advances, this study reveals previously unreported physical insights into the dipole behavior and interfacial diffusion in ultrathin Hf/Zr multilayers. These results establish HZHA as an RMG-compatible, V_th-tunable, low-EOT dielectric platform capable of supporting logic scaling beyond the 1 nm frontier.

We perform a comprehensive study of memory retention characteristics in ferroelectric field-effect transistors with different engineered gate stacks designed to achieve a large memory window (MW) for NAND storage application. Through this study, we show that the widely reported retention loss in these band-engineered FEFETs can be mitigated by optimizing the position of the dielectric insert. Specifically, placing the dielectric insert in the middle of the FE stack (tunnel dielectric layer, TDL) leads to excellent retention while increasing the MW to a quad-level-cell compatible level (≥ 7.5V). This enhanced retention is enabled by the potential wells at the TDL-FE interfaces that energetically secure the MW-enhancing charges and prevent their detrapping. In contrast, placing the dielectric insert on the gate side (gate blocking layer, GBL), while maximizing the MW, compromises retention due to the detrapping of the trapped charges at the GBL-FE interface through the GBL.

We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al ₂ O ₃ layer within the ferroelectric (FE) Hf _0.5 Zr _0.5 O ₂ layer in the gate stack significantly enhances the memory window (MW), achieving levels suitable for quad-level cell operation (approximately 7.5 V) while operating at a reduced write voltage (below 15 V). Despite these improvements, the band-engineered FEFET exhibits similar pass disturb characteristics in the PGM state as a standard FEFET with an FE-only gate stack. To improve the disturb characteristics, we introduce and validate a periodic refresh-based disturb mitigation scheme, analogous to strategies employed in SSD controllers and flash memory managers for traditional charge trap flash-based NAND chips. This mitigation scheme reduces disturb in the PGM state from ~28% to approximately ~4% in the band-engineered FEFETs, enabling large memory window, lowdisturb operation.