Huan Wang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Huan Wang has a total of 15 co-authors. Here are the top co-authors by number of shared publications:
- Hang Li
National Key Laboratory of Microwave Imaging Technology, Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China
4 shared publications - Xingdong Liang
National Key Laboratory of Microwave Imaging Technology, Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China
4 shared publications - Yanlei Li
National Key Laboratory of Microwave Imaging Technology, Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China
3 shared publications - Zhiyu Jiang
National Key Laboratory of Microwave Imaging Technology, Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China
3 shared publications - Jihao Xin
National Key Laboratory of Microwave Imaging Technology, Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China
2 shared publications - Xiangxi Bu
National Key Laboratory of Microwave Imaging Technology, Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China
2 shared publications
Latest Publications
- Open Access
- 6 May 2026
- Published by MDPI AG in Electronics
- Vol. 15 (9) , 1962
An Elevation Ambiguity Resolution Method Based on Prior Elevation Constraints for Small UAV-Borne Distributed TomoSAR
Small unmanned aerial vehicle (UAV)-borne distributed tomographic synthetic aperture radar (TomoSAR) systems offer flexible baseline configurations and low deployment cost, making them attractive for rapid and high-resolution three-dimensional (3D) reconstruction. However, the distance between adjacent channels placed on different UAVs is relatively large due to the flight safety spacing considerations. This leads to high sidelobes in the elevation point spread function (PSF) within the reconstruction range. Meanwhile, atmospheric turbulence may cause UAVs to deviate from their predefined trajectories, making it difficult to suppress sidelobes through baseline optimization. Large baselines may also introduce spatial decorrelation between channels, which gives rise to random phase noise in the interferometric phase and further aggravates elevation ambiguity by increasing the sidelobe level of the PSF. To address this problem, this paper proposes an elevation ambiguity resolution method based on neighborhood-adaptive elevation priors. In the proposed method, a window function is constructed from reconstruction results of neighboring pixels and incorporated into the reconstruction process to suppress the interference caused by high sidelobes. In this way, the probability of correct target reconstruction is improved. The effectiveness and robustness of the proposed method are validated using both simulations and real measured data. Experimental results obtained with a C-band small UAV-borne distributed TomoSAR system show that the proposed method effectively suppresses ambiguity and enables ambiguity-free reconstruction of target buildings. Statistical analysis further demonstrates that the number of ambiguous points produced by the proposed algorithm is only one-fifth of that produced by the conventional OMP method.
- 6 May 2026
- Published by MDPI AG in Electronics
- Vol. 15 (9) , 1962
Open AccessAn Elevation Ambiguity Resolution Method Based on Prior Elevation Constraints for Small UAV-Borne Distributed TomoSAR
Small unmanned aerial vehicle (UAV)-borne distributed tomographic synthetic aperture radar (TomoSAR) systems offer flexible baseline configurations and low deployment cost, making them attractive for rapid and high-resolution three-dimensional (3D) reconstruction. However, the distance between adjacent channels placed on different UAVs is relatively large due to the flight safety spacing considerations. This leads to high sidelobes in the elevation point spread function (PSF) within the reconstruction range. Meanwhile, atmospheric turbulence may cause UAVs to deviate from their predefined trajectories, making it difficult to suppress sidelobes through baseline optimization. Large baselines may also introduce spatial decorrelation between channels, which gives rise to random phase noise in the interferometric phase and further aggravates elevation ambiguity by increasing the sidelobe level of the PSF. To address this problem, this paper proposes an elevation ambiguity resolution method based on neighborhood-adaptive elevation priors. In the proposed method, a window function is constructed from reconstruction results of neighboring pixels and incorporated into the reconstruction process to suppress the interference caused by high sidelobes. In this way, the probability of correct target reconstruction is improved. The effectiveness and robustness of the proposed method are validated using both simulations and real measured data. Experimental results obtained with a C-band small UAV-borne distributed TomoSAR system show that the proposed method effectively suppresses ambiguity and enables ambiguity-free reconstruction of target buildings. Statistical analysis further demonstrates that the number of ambiguous points produced by the proposed algorithm is only one-fifth of that produced by the conventional OMP method.
- Open Access
- 27 April 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (5) , 535
SpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators
Lightweight Unmanned Aerial Vehicles (UAVs) have limited space, low payload capacity, and constrained power supply capabilities. Therefore, their payloads are constrained by size, weight, and power (SWaP). Thus, designing edge-side signal processing architectures for the payloads of UAVs faces severe challenges. Traditional ASIC design based on manual optimization struggles to meet the demands of low latency and low resource occupancy in edge-side applications. To address this challenge, this paper proposes a signal processing hardware accelerator architecture design framework with algorithm-hardware co-design. The framework employs a cross-level dataflow graph representation to formally capture task characteristics. Reconfigurable dataflow templates and reusable operator IP components are systematically constructed based on this representation. Through multi-objective design space exploration, the framework achieves Pareto-optimal mapping from algorithmic specifications to hardware implementations. Finally, automatic generation of top-level hardware descriptions enables rapid FPGA-based prototyping and functional validation. Taking synthetic aperture radar (SAR) imaging as a study example, compared with non-reconfigurable architectures, this scheme reduces the equivalent gate count by 51.4% without increasing processing latency. Compared with a conventional reconfigurable dataflow architecture, the design improves energy efficiency from 12.8 MS/J to 16.0 MS/J, representing a 25.4% enhancement, while also scaling the supported data processing size by a factor of 4×. It provides a high-performance and scalable hardware acceleration solution for lightweight edge-side computing platforms.
- 27 April 2026
- Published by MDPI AG in Micromachines
- Vol. 17 (5) , 535
Open AccessSpChipADF: An Architecture Design Framework for Radar Signal Processing Hardware Accelerators
Lightweight Unmanned Aerial Vehicles (UAVs) have limited space, low payload capacity, and constrained power supply capabilities. Therefore, their payloads are constrained by size, weight, and power (SWaP). Thus, designing edge-side signal processing architectures for the payloads of UAVs faces severe challenges. Traditional ASIC design based on manual optimization struggles to meet the demands of low latency and low resource occupancy in edge-side applications. To address this challenge, this paper proposes a signal processing hardware accelerator architecture design framework with algorithm-hardware co-design. The framework employs a cross-level dataflow graph representation to formally capture task characteristics. Reconfigurable dataflow templates and reusable operator IP components are systematically constructed based on this representation. Through multi-objective design space exploration, the framework achieves Pareto-optimal mapping from algorithmic specifications to hardware implementations. Finally, automatic generation of top-level hardware descriptions enables rapid FPGA-based prototyping and functional validation. Taking synthetic aperture radar (SAR) imaging as a study example, compared with non-reconfigurable architectures, this scheme reduces the equivalent gate count by 51.4% without increasing processing latency. Compared with a conventional reconfigurable dataflow architecture, the design improves energy efficiency from 12.8 MS/J to 16.0 MS/J, representing a 25.4% enhancement, while also scaling the supported data processing size by a factor of 4×. It provides a high-performance and scalable hardware acceleration solution for lightweight edge-side computing platforms.
- Open Access
- 29 June 2025
- Published by MDPI AG in Remote Sensing
- Vol. 17 (13) , 2232
Improved Real-Time SPGA Algorithm and Hardware Processing Architecture for Small UAVs
Real-time Synthetic Aperture Radar (SAR) imaging for small Unmanned Aerial Vehicles (UAVs) has become a significant research focus. However, limitations in Size, Weight, and Power (SwaP) restrict the imaging quality and timeliness of small UAV-borne SAR, limiting its practical application. This paper presents a non-iterative real-time Feature Sub-image Based Stripmap Phase Gradient Autofocus (FSI-SPGA) algorithm. The FSI-SPGA algorithm combines 2D Constant False Alarm Rate (CFAR) for coarse point selection and spatial decorrelation for refined point selection. This approach enables the accurate extraction of high-quality scattering points. Using these points, the algorithm constructs a feature sub-image containing comprehensive phase error information and performs a non-iterative phase error estimation based on this sub-image. To address the multifunctional, low-power, and real-time requirements of small UAV SAR, we designed a highly efficient hybrid architecture. This architecture integrates dataflow reconfigurability and dynamic partial reconfiguration and is based on an ARM + FPGA platform. It is specifically tailored to the computational characteristics of the FSI-SPGA algorithm. The proposed scheme was assessed using data from a 6 kg small SAR system equipped with centimeter-level INS/GPS. For SAR images of size 4096 × 12,288, the FSI-SPGA algorithm demonstrated a 6 times improvement in processing efficiency compared to traditional methods while maintaining the same level of precision. The high-efficiency reconfigurable ARM + FPGA architecture processed the algorithm in 6.02 s, achieving 12 times the processing speed and three times the energy efficiency of a single low-power ARM platform. These results confirm the effectiveness of the proposed solution for enabling high-quality real-time SAR imaging under stringent SwaP constraints.
- 29 June 2025
- Published by MDPI AG in Remote Sensing
- Vol. 17 (13) , 2232
Open AccessImproved Real-Time SPGA Algorithm and Hardware Processing Architecture for Small UAVs
Real-time Synthetic Aperture Radar (SAR) imaging for small Unmanned Aerial Vehicles (UAVs) has become a significant research focus. However, limitations in Size, Weight, and Power (SwaP) restrict the imaging quality and timeliness of small UAV-borne SAR, limiting its practical application. This paper presents a non-iterative real-time Feature Sub-image Based Stripmap Phase Gradient Autofocus (FSI-SPGA) algorithm. The FSI-SPGA algorithm combines 2D Constant False Alarm Rate (CFAR) for coarse point selection and spatial decorrelation for refined point selection. This approach enables the accurate extraction of high-quality scattering points. Using these points, the algorithm constructs a feature sub-image containing comprehensive phase error information and performs a non-iterative phase error estimation based on this sub-image. To address the multifunctional, low-power, and real-time requirements of small UAV SAR, we designed a highly efficient hybrid architecture. This architecture integrates dataflow reconfigurability and dynamic partial reconfiguration and is based on an ARM + FPGA platform. It is specifically tailored to the computational characteristics of the FSI-SPGA algorithm. The proposed scheme was assessed using data from a 6 kg small SAR system equipped with centimeter-level INS/GPS. For SAR images of size 4096 × 12,288, the FSI-SPGA algorithm demonstrated a 6 times improvement in processing efficiency compared to traditional methods while maintaining the same level of precision. The high-efficiency reconfigurable ARM + FPGA architecture processed the algorithm in 6.02 s, achieving 12 times the processing speed and three times the energy efficiency of a single low-power ARM platform. These results confirm the effectiveness of the proposed solution for enabling high-quality real-time SAR imaging under stringent SwaP constraints.
- Open Access
- 28 February 2025
- Published by MDPI AG in Electronics
- Vol. 14 (5) , 983
Robust Synchronization Error Estimation Under Multipath Fading in Distributed SAR
Unmanned Aerial Vehicle (UAV)-based distributed Synthetic Aperture Radar (SAR) is a current research focus. Phase synchronization is crucial for eliminating the non-coherence of distributed systems. However, as the number of UAVs increases, fast time-varying multipath effects caused by rotors can lead to multipath fading. This degrades the signal-to-noise ratio (SNR) of the synchronization link and distorts the synchronization waveform. It further breaks the reciprocity of the dual one-way synchronization link, ultimately degrading phase synchronization accuracy. We propose a robust method for spike detection and error propagation to improve phase synchronization precision. Using the Hampel filter, we detect pulse peak position jitter and remove observations from anomalous links. We then use data fusion based on minimum variance to recover synchronization errors in these links, leveraging the redundancy in synchronization phase matrices. The effectiveness of the proposed method is confirmed through flight test data from a four-UAV distributed TomoSAR experiment. Compared to the maximum-peak detection method, the phase accuracy is improved from 12.84 deg to 0.61 deg. This method supports the application of distributed SAR.
- 28 February 2025
- Published by MDPI AG in Electronics
- Vol. 14 (5) , 983
Open AccessRobust Synchronization Error Estimation Under Multipath Fading in Distributed SAR
Unmanned Aerial Vehicle (UAV)-based distributed Synthetic Aperture Radar (SAR) is a current research focus. Phase synchronization is crucial for eliminating the non-coherence of distributed systems. However, as the number of UAVs increases, fast time-varying multipath effects caused by rotors can lead to multipath fading. This degrades the signal-to-noise ratio (SNR) of the synchronization link and distorts the synchronization waveform. It further breaks the reciprocity of the dual one-way synchronization link, ultimately degrading phase synchronization accuracy. We propose a robust method for spike detection and error propagation to improve phase synchronization precision. Using the Hampel filter, we detect pulse peak position jitter and remove observations from anomalous links. We then use data fusion based on minimum variance to recover synchronization errors in these links, leveraging the redundancy in synchronization phase matrices. The effectiveness of the proposed method is confirmed through flight test data from a four-UAV distributed TomoSAR experiment. Compared to the maximum-peak detection method, the phase accuracy is improved from 12.84 deg to 0.61 deg. This method supports the application of distributed SAR.