Dominic Leclerc

Spin qubits need to operate within a very precise voltage space around charge state transitions to achieve high-fidelity gates. However, the stability diagrams that allow the identification of the desired charge states are long to acquire. Moreover, the voltage space to search for the desired charge state increases quickly with the number of qubits. Therefore, faster stability diagram acquisitions are needed to scale up a spin qubit quantum processor. Currently, most methods focus on more efficient data sampling. Our approach shows a significant speedup by combining measurement speedup and a reduction in the number of measurements needed to tune a quantum dot device. Using an autotuning algorithm based on a neural network and faster measurements by harnessing the FPGA embedded in Keysight's Quantum Engineering Toolkit (QET), the measurement time of stability diagrams has been reduced by a factor of 9.8. This led to an acceleration factor of 2.2 for the total initialization time of a SiGe quantum dot into the single-electron regime, which is limited by the Python code execution.

We report on the first cryogenic characterization of a nMOS nanosheet transistor down to 1.2 K. We demonstrate that the device operates at low temperatures both in the transistor regime with improved DC characteristics (subthreshold swing) and in the quantum regime with adjustable charge occupation of the quantum dot down to a single electron. We further perform extensive low-frequency charge noise measurements in the quantum dot regime over a broad range of charge occupation numbers and observe low average charge noise of ⟨S0⟩ = 28 ± 10 μeV/ √ Hz at 1 Hz. These results demonstrate that nanosheet transistors are promising for large scale quantum/ classical co-integration of CMOS devices for quantum information processing applications.