Chunlei Li

Through Glass Via (TGV) technology has emerged as a promising solution for advanced packaging. While glass offers lower dielectric loss than silicon, its lower thermal conductivity raises concerns about electro-thermal coupling effects in high-power, high-frequency applications. Therefore, this study conducted an electro-thermal co-design of TGV grounded Coplanar Waveguide (CPW) and Radio Frequency (RF) TGV connected CPW structures. A high-power test platform was developed to investigate the electrical and thermal performance of these structures. The temperature distribution mechanism under high-power conditions was revealed. Under high power and high frequency, the decrease in surface conductivity affected by surface state and film layer composition leads to increased loss, triggering temperature rise and forming an electrothermal coupling loop. Under continuous wave operation (5–20 W), the temperature rise reaches 92.4 °C while insertion loss increases by only 0.4 dB. Under pulsed wave operation (25–100 W, 2.5% duty cycle), the temperature rise is merely 2.1 °C with insertion loss increasing by 0.3 dB. The quadruple-redundant design and reduces heat flux density, preventing localized hotspot formation. The pulse intervals suppress thermal accumulation, leading to lower temperature rise. Therefore, continuous wave applications should prioritize thermal management, while pulsed wave applications can focus on electrical performance optimization.

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectrics. The fineness and complexity of structures, combined with the temperature-dependent and viscoelastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while the PI material properties were extracted via inverse fitting based on thermal warpage measurements. The warpage prediction results were compared against experimental data using the maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and through-silicon via (TSV)/through-glass via (TGV) interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate the copper ratios of four RDLs with the wafer warpages for a specific process scenario, demonstrating the potential for wafer-level warpage control through copper ratio regulation in RDLs.

The development of chip manufacturing and advanced packaging technologies has significantly changed redistribution layers (RDLs), leading to shrinking line width/spacing, increasing the number of build-up layers and package size, and introducing organic materials such as polyimide (PI) for dielectric. The fineness and complexity of structures, combined with the temperature-dependent and viscoplastic properties of organic materials, make it increasingly difficult to predict the thermo-mechanical behavior of wafer-level Cu-PI RDL structures, posing a severe challenge in warpage prediction. This study models and simulates the thermo-mechanical response during the manufacturing process of Cu-PI RDL at the wafer level. A cross-scale wafer-level equivalent model was constructed using a two-level partitioning method, while PI material properties were extracted via inverse fitting based on thermal warpage measurements. Warpage prediction results were compared against experimental data using maximum warpage as the indicator to validate the extracted PI properties, yielding errors under less than 10% at typical process temperatures. The contribution of RDL build-up, wafer backgrinding, chemical mechanical polishing (CMP), and TSV/TGV interposers to the warpage was also analyzed through simulation, providing insight for process risk evaluation. Finally, an artificial neural network was developed to correlate copper ratios of four RDL layers with wafer warpages for a specific process scenario, offering a potential direction for layout design optimization.