Yupeng Hu
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Yupeng Hu has a total of 8 co-authors. Here are the top co-authors by number of shared publications:
- Qi Sun
Zhejiang University, Hangzhou, China
2 shared publications Cheng Zhuo
College of Integrated Circuits, Zhejiang University, Hangzhou, China
1 shared publication- Jindong Tu
The Chinese University of Hong Kong, Shenzhen, Shenzhen, Guangdong, China
1 shared publication - Shucheng Huang
Jiangsu University of Science and Technology
1 shared publication - Tinghuan Chen
The Chinese University of Hong Kong, Shenzhen, Shenzhen, Guangdong, China
1 shared publication - Xulin Zhang
Zhejiang University, Hangzhou, Zhejiang, China
1 shared publication
Latest Publications
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
FUSE-TCAD: A Diffusion-Based Multi-Field Surrogate for High-Fidelity TCAD Device Simulation
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessFUSE-TCAD: A Diffusion-Based Multi-Field Surrogate for High-Fidelity TCAD Device Simulation
- 15 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 44 (11) , 4433-4437
Hierarchical Behavioral Learning-Based Dynamic Electromigration Analysis for Signal Networks
In this work, we propose a novel post-layout netlist simplification, modeling, and agile electromigration (EM) analysis framework. First, we implement a hierarchical parasitic extraction strategy to partition the top-level post-layout netlist into functional modules, followed by a worst-case circuit analysis to quickly identify wires with potential for EM violations within each module. Next, the feedforward neural networks (FFNs) and long short-term memory (LSTM) models are employed to construct circuit behavioral models encompassing the input-output behavior and current responses of specified internal nodes. These models are subsequently converted into Verilog-A format for transistor-level simulation. Finally, we substitute the modules with generated Verilog-A models to reduce the circuit complexity. Our framework can significantly accelerate the simulation and EM analysis under different excitation signals. The experiments show that our framework yields up to $38.02\times $ speedup in simulation time required for transistor-level EM analysis over the commercial tool, together with excellent accuracy.
- 15 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 44 (11) , 4433-4437
Hierarchical Behavioral Learning-Based Dynamic Electromigration Analysis for Signal Networks
In this work, we propose a novel post-layout netlist simplification, modeling, and agile electromigration (EM) analysis framework. First, we implement a hierarchical parasitic extraction strategy to partition the top-level post-layout netlist into functional modules, followed by a worst-case circuit analysis to quickly identify wires with potential for EM violations within each module. Next, the feedforward neural networks (FFNs) and long short-term memory (LSTM) models are employed to construct circuit behavioral models encompassing the input-output behavior and current responses of specified internal nodes. These models are subsequently converted into Verilog-A format for transistor-level simulation. Finally, we substitute the modules with generated Verilog-A models to reduce the circuit complexity. Our framework can significantly accelerate the simulation and EM analysis under different excitation signals. The experiments show that our framework yields up to $38.02\times $ speedup in simulation time required for transistor-level EM analysis over the commercial tool, together with excellent accuracy.