Beyza Dabak
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Beyza Dabak has a total of 15 co-authors. Here are the top co-authors by number of shared publications:
- Robert Calderbank
Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA
7 shared publications - Venkatesh Khammammetti
Electrical and Computer Engineering Department Duke University Durham NC USA
3 shared publications - Ahmed Hareedy
The Computer Science Department with Duke University 27708 Durham North Carolina USA
2 shared publications - Alessandro Mirri
Department of Electrical, Electronic, and Information Engineering, University of Bologna, Bologna, Italy
2 shared publications - Enrico Paolini
CNIT/WiLab, DEI, University of Bologna, Cesena, Italy
2 shared publications - Krishna R. Narayanan
Department of Electrical and Computer Engineering, Texas A&M University, College Station, USA
2 shared publications
Latest Publications
- Open Access
- 7 January 2026
- Published by Springer Nature in Journal on Advances in Signal Processing
- Vol. 2026 (1)
Zak-OTFS-based coded random access for uplink mMTC
- 7 January 2026
- Published by Springer Nature in Journal on Advances in Signal Processing
- Vol. 2026 (1)
Open AccessZak-OTFS-based coded random access for uplink mMTC
- Open Access
Zak-OTFS Based Coded Random Access for Uplink mMTC
This paper proposes a grant-free coded random access (CRA) scheme for uplink massive machine-type communications (mMTC), based on Zak-orthogonal time frequency space (Zak-OTFS) modulation in the delay-Doppler domain. The scheme is tailored for doubly selective wireless channels, where conventional orthogonal frequency-division multiplexing (OFDM)-based CRA suffers from unreliable inter-slot channel prediction due to time-frequency variability. By exploiting the predictable nature of Zak-OTFS, the proposed approach enables accurate channel estimation across slots, facilitating reliable successive interference cancellation across user packet replicas. A fair comparison with an OFDM-based CRA baseline shows that the proposed scheme achieves significantly lower packet loss rates under high mobility and user density. Extensive simulations over the standardized Veh-A channel confirm the robustness and scalability of Zak-OTFS-based CRA, supporting its applicability to future mMTC deployments.
Open AccessZak-OTFS Based Coded Random Access for Uplink mMTC
This paper proposes a grant-free coded random access (CRA) scheme for uplink massive machine-type communications (mMTC), based on Zak-orthogonal time frequency space (Zak-OTFS) modulation in the delay-Doppler domain. The scheme is tailored for doubly selective wireless channels, where conventional orthogonal frequency-division multiplexing (OFDM)-based CRA suffers from unreliable inter-slot channel prediction due to time-frequency variability. By exploiting the predictable nature of Zak-OTFS, the proposed approach enables accurate channel estimation across slots, facilitating reliable successive interference cancellation across user packet replicas. A fair comparison with an OFDM-based CRA baseline shows that the proposed scheme achieves significantly lower packet loss rates under high mobility and user density. Extensive simulations over the standardized Veh-A channel confirm the robustness and scalability of Zak-OTFS-based CRA, supporting its applicability to future mMTC deployments.
- Open Access
Low-Energy Line Codes for On-Chip Networks
Energy is a primary constraint in processor design, and much of that energy is consumed in on-chip communication. Communication can be intra-core (e.g., from a register file to an ALU) or inter-core (e.g., over the on-chip network). In this paper, we use the on-chip network (OCN) as a case study for saving on-chip communication energy. We have identified a new way to reduce the OCN's link energy consumption by using line coding, a longstanding technique in information theory. Our line codes, called Low-Energy Line Codes (LELCs), reduce energy by reducing the frequency of voltage transitions of the links, and they achieve a range of energy/performance trade-offs.
Open AccessLow-Energy Line Codes for On-Chip Networks
Energy is a primary constraint in processor design, and much of that energy is consumed in on-chip communication. Communication can be intra-core (e.g., from a register file to an ALU) or inter-core (e.g., over the on-chip network). In this paper, we use the on-chip network (OCN) as a case study for saving on-chip communication energy. We have identified a new way to reduce the OCN's link energy consumption by using line coding, a longstanding technique in information theory. Our line codes, called Low-Energy Line Codes (LELCs), reduce energy by reducing the frequency of voltage transitions of the links, and they achieve a range of energy/performance trade-offs.
- Open Access
Zak-OTFS and LDPC Codes
Orthogonal Time Frequency Space (OTFS) is a framework for communications and active sensing that processes signals in the delay-Doppler (DD) domain. It is informed by 6G propagation environments, where Doppler spreads measured in kHz make it more and more difficult to estimate channels, and the standard model-dependent approach to wireless communication is starting to break down. We consider Zak-OTFS where inverse Zak transform converts information symbols mounted on DD domain pulses to the time domain for transmission. Zak-OTFS modulation is parameterized by a delay period $τ_{p}$ and a Doppler period $ν_{p}$, where the product $τ_{p}ν_{p}=1$. When the channel spread is less than the delay period, and the Doppler spread is less than the Doppler period, the Zak-OTFS input-output relation can be predicted from the response to a single pilot symbol. The highly reliable channel estimates concentrate around the pilot location, and we configure low-density parity-check (LDPC) codes that take advantage of this prior information about reliability. It is advantageous to allocate information symbols to more reliable bins in the DD domain. We report simulation results for a Veh-A channel model where it is not possible to resolve all the paths, showing that LDPC coding extends the range of Doppler spreads for which reliable model-free communication is possible. We show that LDPC coding reduces sensitivity to the choice of transmit filter, making bandwidth expansion less necessary. Finally, we compare BER performance of Zak-OTFS to that of a multicarrier approximation (MC-OTFS), showing LDPC coding amplifies the gains previously reported for uncoded transmission.Open AccessZak-OTFS and LDPC Codes
Orthogonal Time Frequency Space (OTFS) is a framework for communications and active sensing that processes signals in the delay-Doppler (DD) domain. It is informed by 6G propagation environments, where Doppler spreads measured in kHz make it more and more difficult to estimate channels, and the standard model-dependent approach to wireless communication is starting to break down. We consider Zak-OTFS where inverse Zak transform converts information symbols mounted on DD domain pulses to the time domain for transmission. Zak-OTFS modulation is parameterized by a delay period $τ_{p}$ and a Doppler period $ν_{p}$, where the product $τ_{p}ν_{p}=1$. When the channel spread is less than the delay period, and the Doppler spread is less than the Doppler period, the Zak-OTFS input-output relation can be predicted from the response to a single pilot symbol. The highly reliable channel estimates concentrate around the pilot location, and we configure low-density parity-check (LDPC) codes that take advantage of this prior information about reliability. It is advantageous to allocate information symbols to more reliable bins in the DD domain. We report simulation results for a Veh-A channel model where it is not possible to resolve all the paths, showing that LDPC coding extends the range of Doppler spreads for which reliable model-free communication is possible. We show that LDPC coding reduces sensitivity to the choice of transmit filter, making bandwidth expansion less necessary. Finally, we compare BER performance of Zak-OTFS to that of a multicarrier approximation (MC-OTFS), showing LDPC coding amplifies the gains previously reported for uncoded transmission. - Open Access
LDPC Decoders Prefer More Reliable Parity Bits: Unequal Data Protection Over BSC
Low-density parity-check (LDPC) codes are specified by graphs, and are the error correction technique of choice in many communications and data storage contexts. Message passing decoders diffuse information carried by parity bits into the payload, and this paper measures the value of engineering parity bits to be more reliable than message bits. We consider the binary symmetric channel (BSC) and measure the impact of unequal data protection on the threshold of a regular LDPC code. Our analysis also includes doping where the parity bits are known to the decoder. We investigate BSC with Gallager-A decoder, with a $3$-level-alphabet decoder, and with a full belief propagation decoder. We demonstrate through theoretical analysis and simulation that non-equiprobable inputs lead to significant improvements both in the threshold and in the speed with which the decoder converges. We also show that all these improvements are possible even with a simple $3$-level-alphabet decoder.
Open AccessLDPC Decoders Prefer More Reliable Parity Bits: Unequal Data Protection Over BSC
Low-density parity-check (LDPC) codes are specified by graphs, and are the error correction technique of choice in many communications and data storage contexts. Message passing decoders diffuse information carried by parity bits into the payload, and this paper measures the value of engineering parity bits to be more reliable than message bits. We consider the binary symmetric channel (BSC) and measure the impact of unequal data protection on the threshold of a regular LDPC code. Our analysis also includes doping where the parity bits are known to the decoder. We investigate BSC with Gallager-A decoder, with a $3$-level-alphabet decoder, and with a full belief propagation decoder. We demonstrate through theoretical analysis and simulation that non-equiprobable inputs lead to significant improvements both in the threshold and in the speed with which the decoder converges. We also show that all these improvements are possible even with a simple $3$-level-alphabet decoder.
- Open Access
The Secret Arithmetic of Patterns: A General Method for Designing Constrained Codes Based on Lexicographic Indexing
Constrained codes are used to prevent errors from occurring in various data storage and data transmission systems. They can help in increasing the storage density of magnetic storage devices, in managing the lifetime of electronic storage devices, and in increasing the reliability of data transmission over wires. We recently introduced families of lexicographically-ordered constrained (LOCO) codes. These codes achieve capacity with simple encoding and decoding, and they are easy to reconfigure. In this paper, we generalize our work on LOCO codes by presenting a systematic method that guides the code designer to build any constrained code based on lexicographic indexing once the finite set of data patterns to forbid is known. In particular, we connect the set of forbidden patterns directly to the cardinality of the code and to the rule that uncovers the index associated with a codeword. By doing that, we reveal the secret arithmetic of patterns, and make the code design significantly easier. We design optimal (rate-wise) constrained codes for the new two-dimensional magnetic recording (TDMR) technology. We show notable performance gains as a result of solely applying the new codes. Moreover, we show how near-optimal constrained codes be designed and used to further reduce complexity.
Open AccessThe Secret Arithmetic of Patterns: A General Method for Designing Constrained Codes Based on Lexicographic Indexing
Constrained codes are used to prevent errors from occurring in various data storage and data transmission systems. They can help in increasing the storage density of magnetic storage devices, in managing the lifetime of electronic storage devices, and in increasing the reliability of data transmission over wires. We recently introduced families of lexicographically-ordered constrained (LOCO) codes. These codes achieve capacity with simple encoding and decoding, and they are easy to reconfigure. In this paper, we generalize our work on LOCO codes by presenting a systematic method that guides the code designer to build any constrained code based on lexicographic indexing once the finite set of data patterns to forbid is known. In particular, we connect the set of forbidden patterns directly to the cardinality of the code and to the rule that uncovers the index associated with a codeword. By doing that, we reveal the secret arithmetic of patterns, and make the code design significantly easier. We design optimal (rate-wise) constrained codes for the new two-dimensional magnetic recording (TDMR) technology. We show notable performance gains as a result of solely applying the new codes. Moreover, we show how near-optimal constrained codes be designed and used to further reduce complexity.
- Open Access
Managing Device Lifecycle: Reconfigurable Constrained Codes for M/T/Q/P-LC Flash Memories
Flash memory devices are winning the competition for storage density against magnetic recording devices. This outcome results from advances in physics that allow storage of more than one bit per cell, coupled with advances in signal processing that reduce the effect of physical instabilities. Constrained codes are used in storage to avoid problematic patterns. Recently, we introduced binary symmetric lexicographically-ordered constrained codes (LOCO codes) for data storage and data transmission. This paper introduces simple constrained codes that support non-binary physical substrates; multi, triple, quad, and the currently-in-development penta-level cell (M/T/Q/P-LC) Flash memories. The new codes can be easily modified if problematic patterns change with time. These codes are designed to mitigate inter-cell interference, which is a critical source of error in Flash devices. The occurrence of errors is a consequence of parasitic capacitances in and across floating gate transistors, resulting in charge propagation from cells being programmed to the highest charge level to neighboring cells being programmed to lower levels. The new codes are called $q$-ary asymmetric LOCO codes (QA-LOCO codes), and the construction subsumes codes previously designed for single-level cell (SLC) Flash devices (A-LOCO codes). QA-LOCO codes work for a Flash device with any number, $q$, of levels per cell. For $q \geq 4$, we show that QA-LOCO codes can achieve rates greater than $0.95 \log_2 q$ information bits per coded symbol. The complexity of encoding and decoding is modest, and reconfiguring a code is as easy as reprogramming an adder. Capacity-achieving rates, affordable encoding-decoding complexity, and ease of reconfigurability support the growing development of M/T/Q/P-LC Flash memory devices, as well as lifecycle management as the characteristics of these devices change with time.Open AccessManaging Device Lifecycle: Reconfigurable Constrained Codes for M/T/Q/P-LC Flash Memories
Flash memory devices are winning the competition for storage density against magnetic recording devices. This outcome results from advances in physics that allow storage of more than one bit per cell, coupled with advances in signal processing that reduce the effect of physical instabilities. Constrained codes are used in storage to avoid problematic patterns. Recently, we introduced binary symmetric lexicographically-ordered constrained codes (LOCO codes) for data storage and data transmission. This paper introduces simple constrained codes that support non-binary physical substrates; multi, triple, quad, and the currently-in-development penta-level cell (M/T/Q/P-LC) Flash memories. The new codes can be easily modified if problematic patterns change with time. These codes are designed to mitigate inter-cell interference, which is a critical source of error in Flash devices. The occurrence of errors is a consequence of parasitic capacitances in and across floating gate transistors, resulting in charge propagation from cells being programmed to the highest charge level to neighboring cells being programmed to lower levels. The new codes are called $q$-ary asymmetric LOCO codes (QA-LOCO codes), and the construction subsumes codes previously designed for single-level cell (SLC) Flash devices (A-LOCO codes). QA-LOCO codes work for a Flash device with any number, $q$, of levels per cell. For $q \geq 4$, we show that QA-LOCO codes can achieve rates greater than $0.95 \log_2 q$ information bits per coded symbol. The complexity of encoding and decoding is modest, and reconfiguring a code is as easy as reprogramming an adder. Capacity-achieving rates, affordable encoding-decoding complexity, and ease of reconfigurability support the growing development of M/T/Q/P-LC Flash memory devices, as well as lifecycle management as the characteristics of these devices change with time.