Analog circuits in ultra-deep-submicron CMOS
Authors:
- A.-J. AnnemaAAA.-J. Annema
- B. NautaBNB. Nauta
- R. van LangeveldeRLR. van Langevelde
- H. TuinhoutHTH. Tuinhout
Top Cited Papers
- 3 January 2005
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 40 (1) , 132-143
Abstract
Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena.Keywords
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