CL-PLAC: A Generalized Design Framework for Nonlinear Functions Using Comparator-Less Piecewise Linear Approximate Computation

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Abstract
In this work, we propose a novel comparator-less piecewise linear approximate computation (CL-PLAC) method with hardware-software co-optimization schemes for a cost-effective implementation of nonlinear functions on VLSI. Unlike previous PLAC approaches suffering from comparator-based indexing overhead, CL-PLAC replaces comparator-based nonuniform segmentation with a LUT-based multi-level approach to scalably support a wide range of precision. To effectively realize CL-PLAC, we introduce a novel sector-wise uniform segmentation algorithm that jointly optimizes segment and sector lengths considering the hardware-level costs. Leveraging the proposed algorithm, we further present dedicated hardware with several hardware-level optimizations, including shift-based coefficient computation and parallel LUT indexing, to efficiently support the sector-wise uniform segmentation scheme. Empirical evaluations demonstrate that, under the same precision constraint, CL-PLAC reduces area-time complexity and energy consumption up to 70.2% and 79.3%, respectively, compared to the state-of-the-art PLAC designs. Further evaluations on a diffusion-based generative model and large language models show that CL-PLAC achieves 65.4% lower ATC and 75.4% lower energy consumption, highlighting its effectiveness for deep-learning applications.
Funding Information
  • National Research Foundation of Korea (RS-2025-02264052)
  • Institute of Information & Communications Technology Planning & Evaluation (RS-2023-00229849)

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