Youngjoo Lee

This paper presents an advanced machine learning (ML) model to calculate the tilt and azimuth angles of passive stylus pens on display panels. Based on real-world sensing data, preprocessing steps were developed to automatically capture data windows centered on the peak-value positions, and a custom convolutional neural network (CNN) was applied to estimate the tilt/azimuth information in detail. Considering the missing data samples in edge areas, novel training and inference procedures are newly introduced by adopting the position-based model selection, successfully increasing the estimation quality by assigning the dedicated CNN model per input data window. Compared to the conventional approaches, experimental results reveal that our optimization methods lead to an attractive ML-based tilt/azimuth calculation by significantly reducing the estimation errors when the input position belongs to edge regions.

The demand for high-precision stylus input in modern human-machine interfaces has highlighted the limitations of traditional electromagnetic resonance (EMR) signal-processing techniques, which often suffer from systematic coordinate bias and degraded linearity under stylus tilt, azimuth variation, and hardware interface. In this work, we present StylusNet, a lightweight deep learning framework tailored for accurate coordinate estimation from EMR stylus signals. Our approach combines a dedicated preprocessing pipeline with automatic gain control (AGC) to enhance signal integrity and a two-stage neural predictor that refines coarse coordinate estimates into high-precision outputs. In addition to conventional point-wise error metrics, we newly introduce linearity-oriented evaluation criteria that quantify bowing and deviation in straight-line drawing, thereby capturing user-perceived accuracy. Experimental validations on three real EMR datasets demonstrate that StylusNet reduces mean coordinate error by up to 87.8% compared to the previous method and significantly improves linearity across diverse tilt, azimuth, and environmental conditions. The model also achieves real-time inference on embedded systems, underscoring its practicality and scalability for precision stylus-enabled input systems.

In this work, we propose a novel comparator-less piecewise linear approximate computation (CL-PLAC) method with hardware-software co-optimization schemes for a cost-effective implementation of nonlinear functions on VLSI. Unlike previous PLAC approaches suffering from comparator-based indexing overhead, CL-PLAC replaces comparator-based nonuniform segmentation with a LUT-based multi-level approach to scalably support a wide range of precision. To effectively realize CL-PLAC, we introduce a novel sector-wise uniform segmentation algorithm that jointly optimizes segment and sector lengths considering the hardware-level costs. Leveraging the proposed algorithm, we further present dedicated hardware with several hardware-level optimizations, including shift-based coefficient computation and parallel LUT indexing, to efficiently support the sector-wise uniform segmentation scheme. Empirical evaluations demonstrate that, under the same precision constraint, CL-PLAC reduces area-time complexity and energy consumption up to 70.2% and 79.3%, respectively, compared to the state-of-the-art PLAC designs. Further evaluations on a diffusion-based generative model and large language models show that CL-PLAC achieves 65.4% lower ATC and 75.4% lower energy consumption, highlighting its effectiveness for deep-learning applications.

To enable the efficient deployment of Large Language Models (LLMs) on resource-constrained devices, recent studies have explored Key-Value (KV) Cache compression, such as quantization and sparsity-based methods. However, prior works suffer from limitations in both accuracy and memory efficiency, as they overlook the structural differences between Key and Value states and the interaction between sparsity-based compression and quantization. Moreover, previous works often underexplored the variability of generated token lengths across requests, leading to inconsistent performance. To address these limitations, we present a new asymmetric, state-aware KV Cache compression pipeline. The proposed pipeline tailors quantization granularity, sparsity-based compression type, and sparsity level to each state guided by our analysis of methodological characteristics and state-specific structural properties. Furthermore, we demonstrate that the accuracy degradation and KV Cache footprint under compression are sensitive to the ordering of different operations, highlighting the need for an order-aware design. Building on our state- and order-specific insights, we assess the influence of individual channels before applying Rotary Positional Embedding (RoPE), and define a new criterion for structured channel pruning, enabling pre-RoPE pruning to mitigate accuracy loss. We also incorporate parameter-reusing techniques and avoid extra decoding-time computation and memory overhead. Experimental results demonstrate that our approach achieves superior accuracy-memory trade-offs and consistent memory savings across sequence lengths in both quantized and non-quantized settings.

Non-binary low-density parity-check (NB-LDPC) codes are a prominent class of error-correction codes, offering superior error-correcting performance compared to their binary counterparts. However, previous NB-LDPC decoders suffer from high processing complexity and significant memory overhead when supporting high-order Galois fields and long codeword lengths. To address these challenges, the proposed decoder leverages the trellis min-max algorithm and adopts a column-layered decoding schedule with on-the-fly message computation to reduce memory requirements. Additionally, the proposed column-layered algorithm shares up-to-date information among columns, enhancing the convergence speed of the baseline design. Considering the structure of high-rate NB-LDPC codes, we introduce multi-column processing with an optimized banked memory architecture while minimizing parallel processing overhead through submodule optimization. Fabricated using a 28-nm CMOS technology, the prototype 4KB 0.9-rate decoder achieves a 1.42-fold improvement in area efficiency compared to state-of-the-art designs. While the proposed design is motivated by the requirements of storage applications, its modular organization and scalable parallelism also allow adaptation to diverse domains such as wireless and optical communications.

Energy efficiency remains a critical challenge in network-on-chip (NoC) based machine learning (ML) accelerators due to high computation and communication costs. Existing NoC optimization techniques often overlook the intrinsic co-optimization between NoC characteristics and the ML model design. We propose NoC-aware mixed precision quantization (NMIX), a two-phase algorithm that jointly minimizes computation and routing energy while preserving model accuracy. The first phase performs a coarse search to identify accuracy-sensitive quantization boundaries, followed by fine-grained precision assignment based on sensitivity and NoC energy profiles. Experiments on image classification tasks with VGG and ResNet demonstrate energy savings of up to 91.5% over FP32 and 57.5% over uniform 8-bit quantization, confirming the scalability and effectiveness of NMIX for energy-efficient ML accelerators.

Targeting the real-time arrhythmia diagnosis on resource-limited edge devices, in this paper, we present a lightweight electrocardiogram classification system using event-driven machine learning processing. A self-personalized anomaly detector based on signal processing is newly developed to dynamically update internal decision criteria from each patient's recent electrocardiogram history, that activates the following machine learning model only for the abnormal cases. A Siamese neural network is adopted to identify detailed arrhythmia classes by comparing features from the self-personalized normal data and the current abnormal input, increasing the classification accuracy. We also develop a simple version of our Siamese model to reduce the number of trainable parameters while preserving the end-to-end classification accuracy. Experimental results show that the proposed event-driven system reduces ML model activations by 74% for normal beats, achieving a classification accuracy of 96.9% comparable to leading solutions. Additionally, it consumes three times less energy and achieves 3.6 times faster processing latency compared to cost-aware method on a mobile GPU platform, enabling extended battery life and real-time analysis on edge devices.