Dynamic Modeling of Parametric Shifts in FinFETs Under Hot Carrier Degradations
- 2 December 2025
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 73 (1) , 63-70
Abstract
This work analyzes the impact of hot carrier degradation (HCD) on the full-IV electrical characteristics of FinFETs and develops a dynamic model. Data analysis shows that shifts in the subthreshold swing (SS), the transconductance ( ${G}_{m}\text {)}$ , and drain-induced barrier lowering (DIBL), besides the threshold voltage ( ${V}_{\text {TH}}\text {)}$ and the on-state current ( ${I}_{\text {on}}\text {)}$ , are presented in FinFETs due to HCD. Correspondingly, four parameters of the FinFET model BSIM-CMG are identified and reformulated with an explicit workload and temporal dependence. An automatic parameter extraction flow with the particle swarm optimization (PSO) algorithm is further developed for an efficient parameterization of the continuous-time model. This aging model is applied to the 16/14- and 7-nm FinFET HCD silicon data, showing its validity in reproducing the full-IV aging characteristics, beyond the ${V}_{\text {TH}}$ -only model. With the dynamic time evolution method (DTEM) to convert it into a discrete-time formulation, the temporal HCD model is implemented into the SPICE simulator through a model interface. Circuit simulations show that the developed dynamic model outperforms the local HCD model in predicting the figure-of-merits, such as SRAM performance and power.Keywords
Funding Information
- National Natural Science Foundation of China (T2293700)
- National Natural Science Foundation of China (T2293703)
- National Natural Science Foundation of China (62474009)
- National Natural Science Foundation of China (62125401)
- Guangdong Basic and Applied Basic Research Foundation (2024B1515020064)
This publication has 18 references indexed in Scilit:
- A Device to Circuit Reliability Framework for BTI and HCD Aging2024
- A Neural Network based Fast Parameter Extraction of Compact Hot Carrier Degradation Model in FinFETs2024
- Understanding Hot Carrier Reliability in FinFET Technology from Trap-based Approach2021
- Lateral profiling of HCI induced damage in ultra-scaled FinFET devices with Id-Vd characteristics2018
- New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability2017
- New observations on the two-stage degradation of hot carrier reliability in high-k/metal-gate MOSFETs2017
- Impact of BTI on dynamic and static power: From the physical to circuit level2017
- The physical mechanism investigation between HK/IL gate stack breakdown and time-dependent oxygen vacancy trap generation in FinFET devices2016
- Hot carrier aging and its variation under use-bias: Kinetics, prediction, impact on Vdd and SRAM2015
- Hot Carrier Degradation in Semiconductor Devices2015