Pengpeng Ren

Time-Dependent Dielectric Breakdown (TDDB) has emerged as a critical reliability concern in Back-End-of-Line (BEOL) interconnects. In Electric Path Generation (EPG) based TDDB analysis, the evolution of metal ion concentration is governed by a Partial Differential Equation (PDE). Traditional numerical methods for solving this equation are time-consuming and demand considerable computational resources, making them impractical for large-scale circuits analysis. To address this challenge, we propose a physics-informed learning framework for fast prediction of ion concentration distributions in large BEOL layouts. The framework represents BEOL patterns as two-dimensional images, partitions large layouts into overlapping sub-graphs for encoding, and predicts transient concentration fields for each sub-graph. Based on the reconstructed full-layout concentration map, the method supports efficient TDDB hotspot analysis. The proposed Physics-Informed Central Emphasized Convolutional Neural Network (PICE-CNN) is applicable to diverse interconnect patterns and operating conditions, including different line widths, line spacings, and supply voltages. Experimental results show that the proposed method achieves up to 357.1× speedup over conventional numerical solvers while maintaining high prediction accuracy, with the mean squared error below 1× 10 ^-4 in the emphasized central region.

With the continuous scaling of integrated circuits, aging effects pose severe challenges to circuits’ timing analysis. Accurately predicting circuit delays after aging, thereby ensuring circuit reliability throughout its lifecycle, becomes increasingly critical. Identifying the critical path plays a crucial role in this procedure. This paper introduces FACT, a framework that integrates a GNN-based mixture of experts with a masked multi-modal attention mechanism to enhance adaptability. FACT dynamically assigns experts based on circuit inputs and leverages masked attention to capture and fuse multi-scale information across nodes, improving its generalization to unseen circuits. To the best of our knowledge, this framework is the first to achieve accurate prediction of cell delay while simultaneously predicting the critical path after aging. Experimental results show that FACT performs well in terms of accuracy, efficiency, interpretability, and transferability. The average prediction precision of cell delay reaches 93.25%, along with the average prediction accuracy of the critical path reaching 97.86%. Therefore, FACT provides a promising approach for the reliability-aware circuit design.

Low-voltage hafnia-based ferroelectric memory is essential but remains challenging because conventional strategies, such as thickness scaling or mean coercive field reduction, often incur leakage or remanent polarization (Pr) penalties. A key but often overlooked factor is that EC is not a single value but exhibits a broad domain-to-domain distribution, whose high-field tail typically determines the voltage required for full polarization switching. Here, we show that narrowing the standard deviation (σ) rather than merely lowering its mean (μ) enables low-voltage switching in Hf0.5Zr0.5O2 capacitors without the usual trade-off in leakage or Pr. This is achieved by tailoring the oxygen dose during atomic layer deposition in a trilayer stack, which compensates for the spatial inhomogeneity of oxygen vacancy and thereby reshapes the local switching landscape. A low operating voltage of 1.5 V is achieved in 10 nm devices with 2Pr of 44 μC/cm2 and a leakage current density of 5 × 10−6 A/cm2. The same strategy remains effective at 6 nm, where an operating voltage of 0.9 V maintains 2Pr above 40 μC/cm2. These results establish a new paradigm for realizing low-voltage HfO2-based FeRAM compatible with advanced logic nodes by engineering σ of the EC distribution.

This article investigates the non-Gaussian threshold voltage (V ${}_{\text {th}}\text {)}$ variability in MOSFETs under cryogenic conditions. The observed behavior is attributed to the strong coupling between work function variation (WFV) and band tail state variation (BTV), which results in a pronounced long-tail distribution in V_th. This coupling significantly amplifies device variability, thereby posing challenges for digital circuit design in cryogenic environments. To model this non-Gaussian distribution, we propose a mixed distribution that covers from room temperature to cryogenic conditions. Finally, a compact model is introduced, which can be integrated into the BSIM framework to simulate the non-Gaussian V_th behavior. The proposed model and insights provide crucial tools for the design of reliable and scalable cryogenic computing systems.

Due to the high local current densities, Through Silicon Vias (TSVs) are susceptible to electromigration (EM) degradation, which reduces the reliability of integrated circuits. Unlike traditional methods for TSV modeling and simulation, this paper introduces a unified hard constraint physics-informed learning neural network approach, called HCPINN, for the transient analysis of electromigration in TSVs by solving the conventional mass balance equation. The proposed method allows simultaneous consideration of atomic depletion and accumulation, effective resistance degradation, electric current evolution, and stress distribution. Specifically, we propose a hard constraint method for solving partial differential equations (PDEs) with general boundary conditions (BCs) for transient TSV electromigration analysis. By using the extra fields derived from the mixed finite element method, we reconstruct the corresponding PDEs by transforming general BCs into linear forms. Based on this derivation, we embed general BCs of mass balance equation into the proposed ansatz and employ sub-networks for the approximation on general BCs. The main neural network is responsible for training the internal part of the problem domain without adding loss terms with BCs, overcoming the convergence issue due to unbalanced gradients among different loss terms. Besides, we theoretically demonstrate that this reformulation of general BCs can stabilize the training process. Experimental results indicate that the proposed HCPINN exhibits superior performance and reduces boundary error in TSV electromigration analysis. Compared to the finite element method, the proposed network achieves approximately more than 70 times faster inference with a minimal mean squared error increase of less than 0.1% under different TSV geometries and varying current density profiles.

This work analyzes the impact of hot carrier degradation (HCD) on the full-IV electrical characteristics of FinFETs and develops a dynamic model. Data analysis shows that shifts in the subthreshold swing (SS), the transconductance ( ${G}_{m}\text {)}$ , and drain-induced barrier lowering (DIBL), besides the threshold voltage ( ${V}_{\text {TH}}\text {)}$ and the on-state current ( ${I}_{\text {on}}\text {)}$ , are presented in FinFETs due to HCD. Correspondingly, four parameters of the FinFET model BSIM-CMG are identified and reformulated with an explicit workload and temporal dependence. An automatic parameter extraction flow with the particle swarm optimization (PSO) algorithm is further developed for an efficient parameterization of the continuous-time model. This aging model is applied to the 16/14- and 7-nm FinFET HCD silicon data, showing its validity in reproducing the full-IV aging characteristics, beyond the ${V}_{\text {TH}}$ -only model. With the dynamic time evolution method (DTEM) to convert it into a discrete-time formulation, the temporal HCD model is implemented into the SPICE simulator through a model interface. Circuit simulations show that the developed dynamic model outperforms the local HCD model in predicting the figure-of-merits, such as SRAM performance and power.

Nanosheet transistors has emerged as a potential structure of semiconductor technology. The introduction of Wrapped-Around Contact (WAC) and Backside Power Delivery Network, particularly the Backside Contact (BSC) in nanosheet transistors, has effectively promotes further scaling. This work contributes to design technology co-optimization (DTCO) for BSC technology by comprehensively exploring the impact of structural innovation, process parameters and dimension parameters. Through electro-thermal coupling simulations, we reveal the significant advantages of Backside Contact with WAC structure in terms of electrothermal properties compared to conventional structures. We also investigate the impact of contact resistivity, contact thermal resistivity, sheet width and number on device and circuit performance. This work provides an inspiration to optimize electro-thermal performance under advanced nodes.