Yongkang Xue

Due to the high local current densities, Through Silicon Vias (TSVs) are susceptible to electromigration (EM) degradation, which reduces the reliability of integrated circuits. Unlike traditional methods for TSV modeling and simulation, this paper introduces a unified hard constraint physics-informed learning neural network approach, called HCPINN, for the transient analysis of electromigration in TSVs by solving the conventional mass balance equation. The proposed method allows simultaneous consideration of atomic depletion and accumulation, effective resistance degradation, electric current evolution, and stress distribution. Specifically, we propose a hard constraint method for solving partial differential equations (PDEs) with general boundary conditions (BCs) for transient TSV electromigration analysis. By using the extra fields derived from the mixed finite element method, we reconstruct the corresponding PDEs by transforming general BCs into linear forms. Based on this derivation, we embed general BCs of mass balance equation into the proposed ansatz and employ sub-networks for the approximation on general BCs. The main neural network is responsible for training the internal part of the problem domain without adding loss terms with BCs, overcoming the convergence issue due to unbalanced gradients among different loss terms. Besides, we theoretically demonstrate that this reformulation of general BCs can stabilize the training process. Experimental results indicate that the proposed HCPINN exhibits superior performance and reduces boundary error in TSV electromigration analysis. Compared to the finite element method, the proposed network achieves approximately more than 70 times faster inference with a minimal mean squared error increase of less than 0.1% under different TSV geometries and varying current density profiles.

This work analyzes the impact of hot carrier degradation (HCD) on the full-IV electrical characteristics of FinFETs and develops a dynamic model. Data analysis shows that shifts in the subthreshold swing (SS), the transconductance ( ${G}_{m}\text {)}$ , and drain-induced barrier lowering (DIBL), besides the threshold voltage ( ${V}_{\text {TH}}\text {)}$ and the on-state current ( ${I}_{\text {on}}\text {)}$ , are presented in FinFETs due to HCD. Correspondingly, four parameters of the FinFET model BSIM-CMG are identified and reformulated with an explicit workload and temporal dependence. An automatic parameter extraction flow with the particle swarm optimization (PSO) algorithm is further developed for an efficient parameterization of the continuous-time model. This aging model is applied to the 16/14- and 7-nm FinFET HCD silicon data, showing its validity in reproducing the full-IV aging characteristics, beyond the ${V}_{\text {TH}}$ -only model. With the dynamic time evolution method (DTEM) to convert it into a discrete-time formulation, the temporal HCD model is implemented into the SPICE simulator through a model interface. Circuit simulations show that the developed dynamic model outperforms the local HCD model in predicting the figure-of-merits, such as SRAM performance and power.

The interaction between hot carrier degradation (HCD) and electrical-induced breakdown (EiB) in FinFETs at advanced technology nodes is investigated for the first time. Unlike previous findings in planar FETs, HCD significantly impacts EiB in FinFETs, with opposite effects on n-and p-type. Our analysis reveals that the competitive mechanism between defect-induced leakage increase and defect-induced electric field reduction is the primary cause of these differences. For nFinFETs, HCD-induced defects lead to significant leakage current and substantial Joule heating, both of which accelerate the breakdown of interconnect M0 metal. Conversely, for pFinFETs, the leakage current increase is negligible, while fixed charges generated in the high-k (HK) layer reduce the internal electric field within the dielectric, thereby slowing down EiB. The study also traces the physical origins of defects caused by HCD, identifying hydroxyl-E^′ (H–E^′) centers in the IL layer and oxygen vacancy (Vo) in the HK layer as key contributors to the differing leakage behaviors of n-and p-FinFETs. To address the reliability challenges posed by HCD on EiB in nFinFETs, a novel M0 metal design methodology that considers the interaction between HCD and EiB is proposed, offering a pathway to improve interconnect reliability for advanced technology nodes.

With the recent industrial adoption of a new low-power standby mode in the sub-word line drivers (SWD), we report a reliability challenge that occurs on p-type pitch transistor in sub-20-nm DRAM technology introduced by the GIDL-state degradation (GSD). It is observed that GSD can surpass the off-state degradation (OSD) stress mode. By separating different types of traps, we clarified the physical mechanism of GSD. Based on the understanding, a defect-based compact model is developed and validated, providing DRAM designers with a tool to find a balance between power consumption and long-term reliability.

A compact electrothermal model of vertical gate-all-around (VGAA) transistors is developed in this work. Owing to the structural asymmetry inherent in VGAA devices, the internal thermal conduction of such devices differs from that of lateral gate-all-around (LGAA) transistors. The self-heating effect (SHE) of VGAA and thermal optimization is investigated through numerical simulation, revealing a 53% decrease in the temperature rise by changing the spacer material from SiO2 to Si3N4. In addition, a physics-based thermal model with geometry dependence is demonstrated, which captures the four-stage temperature traces of VGAA and supports technology optimization. The physics-based thermal model was verified through TCAD simulation and was subsequently employed to assess the electrothermal performance at the device-circuit level.

Based on the sub-20-nm DRAM technology, the peripheral transistors under stress in the subthreshold-state degradation (SSD) are investigated for the first time. A completely new phenomenon, two-stage degradation, is observed, which can not only exhibit large degradation even comparable to channel hot carrier (CHC) stress mode but also introduce severe device-to-device variation. The novel mechanism of positive-feedback-induced second-impact-ionization is revealed as the root causing such an issue. Based on the understanding, a defect-based two-stage new model is proposed and validated. Since SSD can occur during every AC switching, they must be taken into consideration in future device- and circuit-level reliability assessments.

Flicker noise has become a critical issue in advanced FinFET technology with the rapid growth of analog/mixed-signal circuits. Due to the increasing variation of flicker noise, the applicability of conventional carrier and mobility fluctuation model faces challenges in the aspects of bias, frequency, and size dependences. In this article, we propose a method to separate the intertwined noise sources. Based on this method, the sources of flicker noise can be well clarified, enabling the modeling of different components independently. Considering the inelastic (de)trapping, quasi-ballistic transport, and access resistance (AR), the modeling method and feature are discussed. It is observed that ignoring noise sources other than oxide traps (OTs) can result in an underestimation of approximately 60% under operating conditions. In addition, the contribution of the OTs depends on the energy distribution of different types of traps. Their origins are also clarified by different characterization techniques and ab initio calculation. Therefore, this work is helpful to the variability-aware circuit design in advanced technology nodes.

With the downscaling of CMOS technology, device aging induced by hot carrier injection and bias temperature instability effects poses severe challenges to timing analysis of digital circuits. In this work, a fast aging-aware timing analysis framework based on temporal–spatial graph neural network (GNN) is proposed for the first time. The temporal–spatial GNN takes gated tanh unit (GTU) as the temporal network to extract devices’ degradation from dynamic biases, and takes inductive GraphSAGE as the spatial network to obtain whole graph information from circuit topology and output circuit aging delay. With comprehensive comparison among the network candidates, the combination of GTU and GraphSAGE presents the highest accuracy in predicting the standard cell aging delay. Owing to the superior features capture capability, this framework significantly improves the aging prediction efficiency under various operation conditions, especially facing the iterations of usage scenario, design version and process design kit. Compared with the conventional flow, the average acceleration ratio of our temporal–spatial network in predicting aging delay is more than 200 times. Furthermore, this framework is demonstrated with ADDER and FIFO circuits in timing analysis at the end of life. Thus, this work is helpful to the aging-aware circuit design in nano-scale technology.

Reliability-and variability-aware design-technology co-optimization (RV-aware DTCO) becomes indispensable with advanced nodes. However, four key issues hinder its practical adoption: the lack of characterization technique that offers both accuracy and efficiency, the lack of defect model with long-term prediction capability, the lack of compact model compatible with most EDA platforms, and the low efficiency in circuit-level prediction to support frequent iterations during co-optimization. Demonstrating with 7-nm technology, this work tackles these issues by developing an efficient characterization method for separating defects, introducing a comprehensive test-data-verified defect-centric physical-based model and an industry-friendly open model interface (OMI)-based compact model, and proposing a machine learning (ML)-assisted approach to accelerate circuit-level prediction. With these achievements, an RV-aware DTCO flow is established and demonstrated on 3-nm gate-all-around (GAA) technology to bridge the material level to the circuit level. The work paves ways in boosting adoption of RV-aware DTCO in both circuit design and process development for ultimate nodes.