A structured and scalable test access architecture for TSV-based 3D stacked ICs
Authors:
- 1 April 2010
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 10930167,p. 269-274
Abstract
New process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a DfT test access architecture for such 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The DfT architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. It adds a die-level wrapper, which is based on IEEE 1500, with the following novel features: (1) dedicated probe pads on the non-bottom dies to facilitate pre-bond die testing, (2) TestElevators that transport test control and data signals up and down during post-bond stack testing, and (3) a hierarchical Wrapper Instruction Register (WIR) chain. The paper also hints at opportunities for optimization and standardization of this architecture.Keywords
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