An Investigation Into the Effects of the Gate Drive Resistance on the Losses of the MOSFET–Snubber–Diode Configuration

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Abstract
This paper presents an investigation into the effects of the gate drive resistance on the losses of the MOSFET-snubberdiode (MSD) configuration commonly used in many power converters. An analytical loss model that takes the circuit stray inductances, MOSFET parasitic capacitances and inductances, and reverse current characteristic of the freewheeling diode into consideration is derived to describe the interactions among the MOSFET, snubber, and freewheeling diode during the switching transients. Two possible turn-ON switching situations, determined by the gate drive part and the power part, respectively, are distinguished in the analysis. It is then used to study the effects of the stray inductances, gate drive resistance and snubber on the switching behaviors, power loss distribution, and voltage stress on the MOSFET in the entire MSD configuration. A sequence of steps will be given to illustrate how an optimal combination of the gate drive resistance and snubber capacitance is determined, in order to minimize the overall loss of the MSD configuration for a maximum permissible voltage stress on the MOSFET. The loss model and method of determining the gate drive resistance and snubber capacitance are evaluated by comparing the theoretical predictions with the experimental results of a 400V, 6A test bench. The performances of the MSD configuration with different types of freewheeling diodes will be studied.

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