An LC-DCO based synthesizable injection-locked PLL with an FoM of −250.3dB
- 20 October 2016
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 197-200
Abstract
This paper presents an LC-DCO based synthesizable injection-locked all-digital phase-locked loop. The superior noise performance of the LC-DCO enables the proposed synthesizable PLL to achieve top performance among the existing designs. Fabricated in a 65nm digital CMOS process, the chip occupies a core area of 0.12mm2. The measured integrated jitter is 0.142ps at a carrier of 3.0GHz while consuming a power of 4.6mW under 1V power supply. It achieves a figure of merit (FoM) of -250.3dB, which is the best for the synthesized PLL so far to the best knowledge of the authors.Keywords
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