Through the Looking-Glass: Sensitive Data Extraction by Optical Probing of Scan Chains
Open Access
- 5 September 2024
- journal article
- Published by Universitatsbibliothek der Ruhr-Universitat Bochum in IACR Transactions on Cryptographic Hardware and Embedded Systems
- Vol. 2024 (4) , 541-568
Abstract
There is an imminent trade-off between an Integrated Circuit (IC)’s testability and its physical security. While Design for Test (DfT) techniques, such as scan chains make the circuit’s physical behavior at runtime observable and easy to control, these techniques form a lucrative class of attack vectors with the potential to compromise the entire security architecture of the Device under Test (DuT). Moreover, with the rapid development of more complex technologies, the need for integration of DfT techniques even intensifies due to the requirement for faster time-to-market of cutting-edge ICs. In this work, we demonstrate that sensitive data can be extracted from the registers once their locations on the chip are identified by exploiting DfT structures and optically probing them — in this case, scan chains, even after the access to test mode is restricted. Furthermore, we show that also an obfuscated scan chain architecture can be fully reconstructed by using tools and techniques encountered in the Failure Analysis (FA) domain.Keywords
This publication has 6 references indexed in Scilit:
- Efficient Key-Gate Placement and Dynamic Scan Obfuscation Towards Robust Logic EncryptionIEEE Transactions on Emerging Topics in Computing, 2019
- IC security and quality improvement by protection of chip backside against hardware attacksMicroelectronics Reliability, 2018
- A novel differential scan attack on advanced DFT structuresACM Transactions on Design Automation of Electronic Systems, 2013
- Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation2008
- Secured Flipped Scan-Chain Model for Crypto-ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007
- Secure Scan: A Design-for-Test Architecture for Crypto ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006