Norbert Herfurth
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Norbert Herfurth has a total of 41 co-authors. Here are the top co-authors by number of shared publications:
- Christian Boit
Technische Universität Berlin
3 shared publications - Elham Amini
Technische Universität Berlin
2 shared publications Tuba Kiyan
Technische Universität Berlin, Berlin, Germany
2 shared publicationsA. Becker
1 shared publication- Alessandro Veronesi
IHP-Leibniz Institute for High Performance Microelectronics, Frankfurt, Germany
1 shared publication - Alexander Steigert
Competence Centre Photovoltaics Berlin Helmholtz‐Zentrum Berlin für Materialien und Energie GmbH 12489 Berlin Germany
1 shared publication
Latest Publications
- Open Access
- 5 September 2024
- Published by Universitatsbibliothek der Ruhr-Universitat Bochum in IACR Transactions on Cryptographic Hardware and Embedded Systems
- Vol. 2024 (4) , 541-568
Through the Looking-Glass: Sensitive Data Extraction by Optical Probing of Scan Chains
There is an imminent trade-off between an Integrated Circuit (IC)’s testability and its physical security. While Design for Test (DfT) techniques, such as scan chains make the circuit’s physical behavior at runtime observable and easy to control, these techniques form a lucrative class of attack vectors with the potential to compromise the entire security architecture of the Device under Test (DuT). Moreover, with the rapid development of more complex technologies, the need for integration of DfT techniques even intensifies due to the requirement for faster time-to-market of cutting-edge ICs. In this work, we demonstrate that sensitive data can be extracted from the registers once their locations on the chip are identified by exploiting DfT structures and optically probing them — in this case, scan chains, even after the access to test mode is restricted. Furthermore, we show that also an obfuscated scan chain architecture can be fully reconstructed by using tools and techniques encountered in the Failure Analysis (FA) domain.
- 5 September 2024
- Published by Universitatsbibliothek der Ruhr-Universitat Bochum in IACR Transactions on Cryptographic Hardware and Embedded Systems
- Vol. 2024 (4) , 541-568
Open AccessThrough the Looking-Glass: Sensitive Data Extraction by Optical Probing of Scan Chains
There is an imminent trade-off between an Integrated Circuit (IC)’s testability and its physical security. While Design for Test (DfT) techniques, such as scan chains make the circuit’s physical behavior at runtime observable and easy to control, these techniques form a lucrative class of attack vectors with the potential to compromise the entire security architecture of the Device under Test (DuT). Moreover, with the rapid development of more complex technologies, the need for integration of DfT techniques even intensifies due to the requirement for faster time-to-market of cutting-edge ICs. In this work, we demonstrate that sensitive data can be extracted from the registers once their locations on the chip are identified by exploiting DfT structures and optically probing them — in this case, scan chains, even after the access to test mode is restricted. Furthermore, we show that also an obfuscated scan chain architecture can be fully reconstructed by using tools and techniques encountered in the Failure Analysis (FA) domain.
- 25 August 2023
- Published by Springer Nature
- p. 500-514
Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins
- 25 August 2023
- Published by Springer Nature
- p. 500-514
Prototyping Reconfigurable RRAM-Based AI Accelerators Using the RISC-V Ecosystem and Digital Twins
- 1 November 2022
- Published by ASM International in EDFA Technical Articles
- Vol. 24 (4) , 4-11
A Guide to Accurate System Calibration and Data Extraction to Increase Significance of Spectral Photon Emission Microscopy Measurements
This article presents and evaluates a calibration method that significantly improves the spectral information that can be extracted from photon emission signals obtained from semiconductor devices. Step-by-step instructions are given for calibrating photon emission microscopes for specific measurements such as device parameters and material band gap. The article also discusses the types of errors that can occur during calibration. Although the procedure presented is used on InGaAs sensors, it applies to all common photon emission detectors.
- 1 November 2022
- Published by ASM International in EDFA Technical Articles
- Vol. 24 (4) , 4-11
A Guide to Accurate System Calibration and Data Extraction to Increase Significance of Spectral Photon Emission Microscopy Measurements
This article presents and evaluates a calibration method that significantly improves the spectral information that can be extracted from photon emission signals obtained from semiconductor devices. Step-by-step instructions are given for calibrating photon emission microscopes for specific measurements such as device parameters and material band gap. The article also discusses the types of errors that can occur during calibration. Although the procedure presented is used on InGaAs sensors, it applies to all common photon emission detectors.
- 25 April 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-12
Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
This paper reviews the evolution of a powerful class of physical attacks against integrated circuits (ICs), developed initially for performing failure analysis (FA) from the IC backside. Over the last two decades, several publications have demonstrated the effectiveness of these techniques in bypassing the IC protection schemes and extracting the stored assets inside secure ICs. In this work, we take a fresh look at such hardware attacks from three different perspectives. First, we will discuss the potential threat of the attacks against modern technologies and demystify a set of wrong beliefs about the attacks' complexity. Second, we review some technical challenges of such attacks from a law enforcement agency's perspective for unraveling crimes and preventing further crimes by criminals involved. Finally, we give an insight into the future development of FA tools and the opportunities for designing effective countermeasures against attacks through the chip backside.
- 25 April 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-12
Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
This paper reviews the evolution of a powerful class of physical attacks against integrated circuits (ICs), developed initially for performing failure analysis (FA) from the IC backside. Over the last two decades, several publications have demonstrated the effectiveness of these techniques in bypassing the IC protection schemes and extracting the stored assets inside secure ICs. In this work, we take a fresh look at such hardware attacks from three different perspectives. First, we will discuss the potential threat of the attacks against modern technologies and demystify a set of wrong beliefs about the attacks' complexity. Second, we review some technical challenges of such attacks from a law enforcement agency's perspective for unraveling crimes and preventing further crimes by criminals involved. Finally, we give an insight into the future development of FA tools and the opportunities for designing effective countermeasures against attacks through the chip backside.
- 17 October 2018
- Published by Springer Nature in Journal of Hardware and Systems Security
- Vol. 2 (4) , 345-352
Assessment of a Chip Backside Protection
- 17 October 2018
- Published by Springer Nature in Journal of Hardware and Systems Security
- Vol. 2 (4) , 345-352
Assessment of a Chip Backside Protection