Low-Latency Unfolded-KES Architecture for Emerging Storage Class Memories

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Abstract
This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.
Funding Information
  • National Research Foundation Grant through the Korean Government (2018R1A4A1025679, 2019R1F1A1060767)
  • Samsung Electronics
  • IC Design Education Center

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