Seungsik Moon

Intelligent reflecting surface (IRS) is one of the promising technologies for next-generation communication systems. Although IRS can enhance the integrity of the transmitted signal, however, it requires additional phase-shift optimization task, potentially increasing the total processing latency of the system. To implement a phase-shift optimization algorithm with low-latency, for the world-first, IRS controller SoC for saving the base station (BS) transmit (TX) antenna power is presented with novel latency reduction techniques; 1) grid-based phase-shift elements with a coarse-grained update, 2) quality-aware approximate processing element with low-resolution saturation arithmetic, 3) optimized data-flow scheduling with double-buffer architecture, and 4) novel low-latency weight update tracking technique. By adopting the proposed techniques, the fully-optimized SoC architecture can enhance the processing latency and energy consumption by 93% and 68%, respectively, compared with the unoptimized SoC architecture. The proposed system is designed and fabricated in 28 nm CMOS technology, where the implementation results show that the fully-optimized SoC system can achieve 43.9 $\mu$ s of processing latency while saving 14.5 dB of TX antenna power for optimizing the $16\times 16$ grid-based IRS architecture with $128\times 8$ MU-MIMO configuration.

In this paper, practical utilization of multiple distributed reconfigurable intelligent surfaces (RISs), which are able to conduct group-specific operations, for multi-group multicasting systems is investigated. To tackle the inter-group interference issue in the multi-group multicasting systems, the block diagonalization (BD)-based beamforming is considered first. Without any inter-group interference after the BD operation, the multiple distributed RISs are operated to maximize the minimum rate for each group. Since the computational complexity of the BD-based beamforming can be too high, a multicasting tailored zero-forcing (MTZF) beamforming technique is proposed to efficiently suppress the inter-group interference, and the novel design for the multiple RISs that makes up for the inevitable loss of MTZF beamforming is also described. Effective closed-form solutions for the loss minimizing RIS operations are obtained with basic linear operations, making the proposed MTZF beamforming-based RIS design highly practical. Numerical results show that the BD-based approach has ability to achieve high sum-rate, but it is useful only when the base station deploys large antenna arrays. Even with the small number of antennas, the MTZF beamforming-based approach outperforms the other schemes in terms of the sum-rate while the technique requires low computational complexity. The results also prove that the proposed techniques can work with the minimum rate requirement for each group.

In this letter, we present a novel deep-learning-based network for MIMO symbol detection, referred to as a momentum-induced detection network, MomentNet. Inspired by the projected gradient descent algorithm, our proposed architecture integrates an additional momentum component to the previous deep-learning detectors. By eliminating redundant values, we have successfully reduced the number of training parameters by half from the baseline network, compensating for the increased computational burden introduced by the incorporation of momentum parameters. Simulation results reveal that the proposed network achieves near-Maximum Likelihood symbol error rate performance with low computational complexity.

In this paper, we propose a cost-efficient phase shift design algorithm for a single-user multiple-input multiple-output wireless system assisted by the intelligent reflecting surface. From the baseline algorithm, two-step hardware-aware algorithm-level optimization techniques are newly introduced to reduce the required number of multiply-accumulate (MAC) operations. For the first step, the low-cost iterative-free matrix is constructed to replace the complicated inversion matrix by exploiting spatial correlatedness among the reflecting elements. Then, the previously designed matrix is approximated by exploiting the diagonally-dominant characteristic of the matrix, further optimizing the computational complexity of the algorithm. Experimental results show that the fully-optimized algorithm with the proposed two-step optimization techniques reduces 98.6% of total cost compared to the baseline algorithm while achieving comparable algorithm-level performance.

This paper investigates a joint user selection, power allocation, and beamforming strategy for maximizing a weighted sum-spectral efficiency in a single-cell multi-user multiple-input multiple-output (MU-MIMO) system. Finding such a joint strategy is challenging due to the non-convexity of the sum-spectral efficiency function for the optimization variables. The recent algorithm, referred to as generalized power iteration precoding (GPIP), allows finding a stationary point in polynomial time for this non-convex problem. GPIP, however, is not scalable to a large-scale MU-MIMO system because of the overwhelming computational complexity. This high complexity makes the hardware energy efficiency worse as the number of antennas and users increases. This paper presents a low-cost simplified GPIP algorithm by jointly taking into account the implementation-level efficiency and algorithm-level performance. The proposed algorithm is to jointly harness the ideas of i ) multiply-accumulate (MAC) operation reduction, ii ) dynamic range reduction, and iii ) low-complexity matrix inversion with approximate computing. Experimental results reveal that the proposed simplified GPIP algorithm reduces the total cost for solving the GPIP algorithm up to 99% while attaining a similar sum-spectral efficiency compared to that of a naive implementation method for GPIP in large-scale MU-MIMO systems.

The number of devices served by baseband stations is constantly increasing due to the rising data traffic in modern communication systems. In order to support large-scale multi-user multiple-input multiple-output (MU-MIMO) systems and achieve their capacity, it is necessary to consider power allocation and user selection along with precoding. This paper introduces a scalable MU-MIMO precoding processor that solves the joint optimization problem for precoding, power allocation, and user selection. We define custom vector instructions and dedicate vector arithmetic operators based on the RV32IM instruction set architecture to efficiently support various MU-MIMO baseband processing scenarios. The proposed vector operators include parallel dual-precision multipliers to enable energy-efficient processing by adjusting the computing resolution of each step without degrading the algorithm-level quality. The proposed processor is fabricated using 28nm CMOS technology and is capable of solving the state-of-the-art joint optimization problem in only 0.51ms for the $64\times 64$ large-scale MU-MIMO configuration. Our processor achieves up to 17.4 times higher processing efficiency compared to previous precoder design, even when supporting the largest number of users and the most complicated algorithm.

In this paper, we propose a cost-efficient beamforming optimization algorithm for multi-user wireless communication systems associated with the intelligent reflecting surface (IRS). From the baseline successive refinement algorithm, which gives a sub-optimal solution for the power minimization problem under the signal-to-interference-plus-noise-ratio (SINR) constraint at each user, several optimization techniques are proposed to reduce the computation complexity while maintaining the algorithm-level performance. To reduce the number of required multiply-accumulate (MAC) operations, we first simplify the complicated matrix inversion by utilizing the channel hardening effect. We also present the two-phase refinement process for the group-level optimization of phase-shift elements, further relaxing the computation complexity as well as the processing latency. Applying the proposed optimization techniques, as a result, numerical results show that the fully-optimized algorithm can reduce the computational costs by up to 89.4% while showing less than 1 dB power loss, leading to the practical solution for the next-generation IRS-aided communication.

In order to effectively reduce buffer energy consumption, which constitutes a significant part of the total energy consumption in a convolutional neural network (CNN), it is useful to apply different amounts of energy conservation effort to the different levels of a CNN as the buffer energy to total energy usage ratios can differ quite substantially across the layers of a CNN. This paper proposes layerwise buffer voltage scaling as an effective technique for reducing buffer access energy. Error-resilience analysis, including inter-layer effects, conducted during design-time is used to determine the specific buffer supply voltage to be used for each layer of a CNN. Then these layer-specific buffer supply voltages are used in the CNN for image classification inference. Error injection experiments with three different types of CNN architectures show that, with this technique, the buffer access energy and overall system energy can be reduced by up to 68.41% and 33.68%, respectively, without sacrificing image classification accuracy.

This paper presents an advanced key-equation solver (KES) algorithm that can reduce the computing latency of BCH decoding for the high-speed storage class memory (SCM). Adopting the unfolding algorithm as a factor of two, compared to the conventional iterative KES scheme, the proposed work potentially halves the number of processing cycles for KES module, which is normally dominates the overall BCH decoding latency. In contrast that the straight-forward unfolding method increases the critical delay, we accelerate the major computing path that is activated at the most of SCM lifetime, preserving the critical delay of the proposed KES module as similar to that of the original one. When the minor cases are detected, the recovery processing is added at the end of the corresponding iteration. In order to reduce the additional energy consumption due to the unfolded architecture, we carefully deactivate the internal modules during the accelerated processing, which only necessitate for the recovery cycle. Implementation results show that the proposed KES architecture greatly reduces the decoding latency of arbitrary BCH decoder, leading to the high-speed and reliable emerging storages.