A 256-Element Slepian Beamforming Accelerator With Analog Compute-In-Memory Multiplication and Accumulation

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Abstract
An analog compute-in-memory Slepian beamforming accelerator is introduced for large-scale MIMO. The design performs complex-valued vector–matrix multiplication in the analog domain to project 256 I/Q inputs into a low-dimensional Slepian subspace and uses a digital backend with 4-tap FIR filters to generate one output beam. A test chip fabricated in 28 nm CMOS demonstrates a 20.5 dB peak-to-sidelobe ratio over a 280 MHz bandwidth while consuming 414 mW.
Funding Information
  • Semiconductor Research Corporation (SRC) through the Center on COGNISENSE and Defense Advanced Research Projects Agency (DARPA) through the Program on OPTIMA

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