Wei-Chun Wang

This work establishes a top-down design methodology for analog compute-in-memory (ACIM) systems that derives circuit-level noise bounds directly from application-specific accuracy constraints. Rather than relying on traditional bottom-up error simulation, we utilize a custom noise injection framework to extract layer-wise noise tolerance thresholds independent of the underlying hardware technology. These abstract thresholds are mathematically translated into minimum computational signal-to-noise ratio (compute SNR) requirements, forming a direct link between algorithm robustness and physical circuit limits. Hardware designers can utilize these SNR targets to reverse-engineer optimal design parameters, including bit precision, array sizing, and data converter scaling. Validated on the Mamba SSM architecture, our framework successfully isolates highly noise-tolerant operations from precision-critical layers, directly informing the design of energy-efficient ACIM systems tailored to specific machine learning workloads.

Mixed-signal CIM faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring Bit-Cell Matched Linearization Interface (BMLI) and Loop-unrolled SAR ADC fabricated in 28 nm CMOS. A 256×256 SRAM array with 8-bit inputs, 8-bit weights achieve 10.16 TOPS peak throughput, 194.59 TOPS/W compute efficiency, 40.46 TOPS/mm² density, and maintains RMSE of 4.3% at 300MHz and 5.6% at 620MHz.

An analog compute-in-memory Slepian beamforming accelerator is introduced for large-scale MIMO. The design performs complex-valued vector–matrix multiplication in the analog domain to project 256 I/Q inputs into a low-dimensional Slepian subspace and uses a digital backend with 4-tap FIR filters to generate one output beam. A test chip fabricated in 28 nm CMOS demonstrates a 20.5 dB peak-to-sidelobe ratio over a 280 MHz bandwidth while consuming 414 mW.

A mixed-precision analog compute-in-memory (Mix-ACIM) is presented for mixed-precision vector-matrix multiplication (VMM). The design features an all-analog current-domain fixed-point VMM with floating-point conversion and feature restoration. A 28nm CMOS test chip shows 41 TOPS/W and 24 TOPS/mm for fixed-point (8-bit input/weight and 12-bit output) and 24.18 TFLOPS/W and 3.3 TFLOPS/mm for 16-bit floating-point equivalent operation.

The demands of modern multi-sensor array applications put stress on every aspect of the processing pipeline, resulting in extremely power-hungry systems. In this paper we investigate a new method of broadband beamforming which, leveraging reduced dimension Slepian processing, has been demonstrated to yield immense power savings. Dimensionality reduction is performed at or near the analog-to-digital interface by applying a small number of measurements, collapsing the array read-out to a greatly reduced number of channels. We then derive two methods of signal estimation from these measurements. A key innovation is that regardless of the estimation method measurements can be taken at low precision. Thereby making the dimensionality reduction process power efficient. We propose a low-precision measurement design algorithm, and show that the resulting beamformers perform well in conventional and adaptive scenarios. To highlight a result, for a $32\times 32$ element uniform planar array 1-bit measurements can achieve in excess of 60 dB of interference cancellation with our method. Finally, we extend our model to subarray beamforming, and show that using Slepian processing in this scenario yields performance benefits over standard implementations.

This paper introduces the Artificial Intelligence-Driven Energy-efficient Analog-to-Learning system (AIDEAL), an AI-enabled in-sensor computing platform designed to enhance energy efficiency in edge devices through in situ data processing. AIDEAL extracts task-relevant features from analog inputs, significantly reducing the data volume for digitization and transmission, by utilizing analog compute-in-memory (ACIM). AIDEAL demonstrates substantial benefits across various applications including image reconstruction, image classification, and object detection. Notably, it achieves 60.2%-80.2% reduction in sensor energy for image classification compared to traditional methods of digitizing and transmitting full input data. We also examine AIDEAL under different feature reduction rates and variations in voltage, and temperature in ACIM. Furthermore, we introduce two algorithmic strategies, feature restoration (FR) and hamming weight based energy aware quantization (HEQA), which enhance accuracy and energy efficiency. These methods result in less than 2% accuracy drop and 37% energy savings compared to baseline, respectively.

This paper introduces a Computing-In-Memory based Spiking Neural Network (SNN) architecture for cryogenic operation of CMOS (Cryo-SNN). The paper demonstrates design strategies to improve energy efficiency of Cryo-SNN by coupling low-voltage operation at cryogenic temperature with innovative design of neuron circuits optimized for cryogenic conditions. By exploiting the enhanced device characteristics of 14 nm FinFET transistors at cryogenic temperatures, our architecture outlines critical adaptations to SNN components for optimal functionality in extreme environments. The circuit simulation using measurement calibrated 14nm FinFET models shows that a Cryo-SNN designed for MNIST classification operates with 4.54X improved energy-delay-product (EDP) over room temperature operation while maintaining similar accuracy. Further, the paper designs an optimized SNN architecture for autonomous health monitoring of miniaturized satellites at cryogenic temperature consuming less than 1mW of power.