Shida Zhang

Mixed-signal CIM faces bit-cell nonlinearity, poor linearity at high frequency, and throughput limits. We present a hybrid pipelined current-domain MS-CIM macro featuring Bit-Cell Matched Linearization Interface (BMLI) and Loop-unrolled SAR ADC fabricated in 28 nm CMOS. A 256×256 SRAM array with 8-bit inputs, 8-bit weights achieve 10.16 TOPS peak throughput, 194.59 TOPS/W compute efficiency, 40.46 TOPS/mm² density, and maintains RMSE of 4.3% at 300MHz and 5.6% at 620MHz.

An analog compute-in-memory Slepian beamforming accelerator is introduced for large-scale MIMO. The design performs complex-valued vector–matrix multiplication in the analog domain to project 256 I/Q inputs into a low-dimensional Slepian subspace and uses a digital backend with 4-tap FIR filters to generate one output beam. A test chip fabricated in 28 nm CMOS demonstrates a 20.5 dB peak-to-sidelobe ratio over a 280 MHz bandwidth while consuming 414 mW.

This paper introduces a Computing-In-Memory based Spiking Neural Network (SNN) architecture for cryogenic operation of CMOS (Cryo-SNN). The paper demonstrates design strategies to improve energy efficiency of Cryo-SNN by coupling low-voltage operation at cryogenic temperature with innovative design of neuron circuits optimized for cryogenic conditions. By exploiting the enhanced device characteristics of 14 nm FinFET transistors at cryogenic temperatures, our architecture outlines critical adaptations to SNN components for optimal functionality in extreme environments. The circuit simulation using measurement calibrated 14nm FinFET models shows that a Cryo-SNN designed for MNIST classification operates with 4.54X improved energy-delay-product (EDP) over room temperature operation while maintaining similar accuracy. Further, the paper designs an optimized SNN architecture for autonomous health monitoring of miniaturized satellites at cryogenic temperature consuming less than 1mW of power.