Optimal Selective Huffman Coding for Test-Data Compression
Authors:
- Emmanouil KalligerosEKEmmanouil Kalligeros
- Dimitris NikolosDNDimitris Nikolos
- 2 July 2007
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 56 (8) , 1146-1152
Abstract
Selective Huffman coding has recently been proposed for efficient test- data compression with low hardware overhead. In this paper, we show that the already proposed encoding scheme is not optimal and we present a new one, proving that it is optimal. Moreover, we compare the two encodings theoretically and we derive a set of conditions which show that, in practical cases, the proposed encoding always offers better compression. In terms of hardware overhead, the new scheme is at least as low-demanding as the old one. The increased compression efficiency, the resulting test-time savings, and the low hardware overhead of the proposed method are also verified experimentally.Keywords
This publication has 17 references indexed in Scilit:
- Efficient Test-Data Compression for IP Cores Using Multilevel Huffman Coding2006
- RL-huffman encoding for test compression and power reduction in scan applicationsACM Transactions on Design Automation of Electronic Systems, 2005
- Embedded Deterministic TestIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004
- Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codesIEEE Transactions on Computers, 2003
- Efficient compression and application of deterministic patterns in a logic BIST architecture2003
- An efficient test vector compression scheme using selective huffman codingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003
- Variable-length input huffman coding for system-on-a-chip testIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003
- A unified approach to reduce soc test data volume, scan power and testing timeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003
- System-on-a-chip test-data compression and decompression architectures based on Golomb codesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001
- Test set compaction algorithms for combinational circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2000